278 lines
10 KiB
C
278 lines
10 KiB
C
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/**
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****************************************************************************************
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*
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* @file uart.h
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*
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* @brief Header file - UART Driver
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*
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****************************************************************************************
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*/
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#ifndef _UART_H_
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#define _UART_H_
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#include <stdint.h>
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#include "rcc.h"
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#include "reg_uart.h"
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/*
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* DEFINES
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****************************************************************************************
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*/
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/// Number of Uart port
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enum uart_port
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{
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UART1_PORT = 0,
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UART2_PORT = 1,
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};
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/// Bits field of line control @see UART_LCR_TypeDef
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enum uart_lcr_bfs
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{
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// data length select - bit[1:0]
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LCR_DATA_BITS_LSB = 0,
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LCD_DATA_BITS_8 = (0x03 << LCR_DATA_BITS_LSB),
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LCD_DATA_BITS_7 = (0x02 << LCR_DATA_BITS_LSB),
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LCD_DATA_BITS_6 = (0x01 << LCR_DATA_BITS_LSB),
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LCD_DATA_BITS_5 = (0x00 << LCR_DATA_BITS_LSB),
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// stop bits select - bit[2]
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LCR_STOP_BITS_LSB = 2,
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LCR_STOP_BITS_1 = (0x00 << LCR_STOP_BITS_LSB),
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LCR_STOP_BITS_2 = (0x01 << LCR_STOP_BITS_LSB),
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// parity mode select - bit[4:3]
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LCR_PARITY_BITS_LSB = 3,
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LCR_PARITY_none = (0x00 << LCR_PARITY_BITS_LSB),
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LCR_PARITY_odd = (0x01 << LCR_PARITY_BITS_LSB),
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LCR_PARITY_even = (0x03 << LCR_PARITY_BITS_LSB),
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// uart receive enable - bit5
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LCR_RXEN_BIT = (1 << 5),
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// receive time out enable - bit8
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LCR_RTOEN_BIT = (1 << 8),
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};
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/// Bits field of fifo control @see UART_FCR_TypeDef
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enum uart_fcr_bfs
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{
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// fifo enable - bit0
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FCR_FIFOEN_BIT = (1 << 0),
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// rx fifo reset - bit1
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FCR_RFRST_BIT = (1 << 1),
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// tx fifo reset - bit2
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FCR_TFRST_BIT = (1 << 2),
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// rx fifo trigger level - bit[5:4]
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FCR_RXTL_LSB = 4,
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FCR_RXTL_1BYTE = (0 << FCR_RXTL_LSB),
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FCR_RXTL_4BYTE = (1 << FCR_RXTL_LSB),
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FCR_RXTL_8BYTE = (2 << FCR_RXTL_LSB),
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FCR_RXTL_14BYTE = (3 << FCR_RXTL_LSB),
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// tx fifo trigger level - bit[7:6]
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FCR_TXTL_LSB = 6,
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FCR_TXTL_1BYTE = (0 << FCR_TXTL_LSB),
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FCR_TXTL_4BYTE = (1 << FCR_TXTL_LSB),
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FCR_TXTL_8BYTE = (2 << FCR_TXTL_LSB),
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FCR_TXTL_14BBYTE = (3 << FCR_TXTL_LSB),
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};
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/// Bits field of uart status @see UART_SR_TypeDef
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enum uart_sr_bfs
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{
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UART_SR_DR_BIT = (1 << 0), // data ready
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UART_SR_OE_BIT = (1 << 1), // overrun error
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UART_SR_PE_BIT = (1 << 2), // parity error
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UART_SR_FE_BIT = (1 << 3), // framing error
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UART_SR_BF_BIT = (1 << 4), // break interrupt
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UART_SR_TBEM_BIT = (1 << 5), // transmit buffer register empty
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UART_SR_TEM_BIT = (1 << 6), // transmitter empty
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UART_SR_RFE_BIT = (1 << 7), // receiver fifo data error
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UART_SR_BUSY_BIT = (1 << 8), // uart busy
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UART_SR_TFNF_BIT = (1 << 9), // transmit fifo not full
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UART_SR_TFEM_BIT = (1 << 10), // transmit fifo empty
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UART_SR_RFNE_BIT = (1 << 11), // receive fifo not empty
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UART_SR_RFF_BIT = (1 << 12), // receive fifo full
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UART_SR_DCTS_BIT = (1 << 13), // delta clear to send
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UART_SR_CTS_BIT = (1 << 14), // clear to send
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UART_SR_ALL_MSK = (0x7FFF), // bit[14:0]
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};
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/// Bits field of uart interrupt @see UART_IER_TypeDef
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enum uart_intr_bfs
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{
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UART_IR_RXRD_BIT = (1 << 0), // receive data available interrupt enable status
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UART_IR_TXS_BIT = (1 << 1), // thr empty interrupt enable status
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UART_IR_RXS_BIT = (1 << 2), // receiver line status interrupt enable status
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UART_IR_MDS_BIT = (1 << 3), // modem status interrupt enable status
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UART_IR_RTO_BIT = (1 << 4), // receiver timeout enable status
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UART_IR_BUSY_BIT = (1 << 5), // busy detect interrupt enable status
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UART_IR_ABE_BIT = (1 << 6), // auto baud rate end interrupt enable status
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UART_IR_ABTO_BIT = (1 << 7), // auto baud rate timeout interrupt enable status
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UART_IR_LINBK_BIT = (1 << 8), // lin break detection interrupt enable status
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UART_IR_TC_BIT = (1 << 9), // transmission complete interrupt enable status
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UART_IR_EOB_BIT = (1 << 10), // end of block interrupt enable status
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UART_IR_CM_BIT = (1 << 11), // character match interrupt enable status
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UART_IR_ALL_MSK = (0x0FFF), // bit[11:0]
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};
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/*
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* MACROS DECLARATION
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****************************************************************************************
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*/
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/// Macro for uart line-control bits configure
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/// @param[in] _dbit data bits value in[8, 7, 6, 5]
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/// @param[in] _sbit stop bits value in[1, 2]
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/// @param[in] _pbit parity mode value in[none, odd, even]
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/// @return the value of the line-control bits @see enum uart_lcr_bfs
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#define LCR_BITS(_dbit, _sbit, _pbit) \
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((uint16_t)(LCD_DATA_BITS_##_dbit | LCR_STOP_BITS_##_sbit | LCR_PARITY_##_pbit))
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/// Macro for uart baudrate divider configure (manual input sysclk_freq)
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/// @param[in] _baud baudrate value, eg. 115200
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/// @param[in] _freq sysclk freq name in[16M, 32M, 48M, 64M] @see enum sys_clk_freq
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/// @return the value of the BRR
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#define BRR_DIV(_baud, _freq) \
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((uint16_t)((SYS_FREQ_##_freq + ((_baud) >> 1)) / (_baud)))
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/// Macro for uart baudrate divider configure (auto get sysclk_freq, more size)
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/// @param[in] _baud baudrate value, eg. 115200
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/// @return the value of the BRR
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#define BRR_BAUD(_baud) \
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((uint16_t)((rcc_sysclk_freq() + ((_baud) >> 1)) / (_baud)))
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/// Common uart params to easy call
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#define LCR_BITS_DFLT LCR_BITS(8, 1, none) // default: 8 DataBits, 1 StopBits, None Parity
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#if (SYS_CLK == 1)
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#define BRR_115200 BRR_DIV(115200, 32M) // default use SYS_FREQ_32M
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#define BRR_921600 BRR_DIV(921600, 32M) // default use SYS_FREQ_32M
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#elif (SYS_CLK == 2)
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#define BRR_115200 BRR_DIV(115200, 48M) // default use SYS_FREQ_48M
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#define BRR_921600 BRR_DIV(921600, 48M) // default use SYS_FREQ_48M
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#elif (SYS_CLK == 3)
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#define BRR_115200 BRR_DIV(115200, 64M) // default use SYS_FREQ_64M
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#define BRR_921600 BRR_DIV(921600, 64M) // default use SYS_FREQ_64M
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#else
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#define BRR_115200 BRR_DIV(115200, 16M) // default use SYS_FREQ_16M
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#define BRR_921600 BRR_DIV(921600, 16M) // default use SYS_FREQ_16M
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#endif //SYS_CLK
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/*
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* FUNCTION DECLARATION
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****************************************************************************************
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*/
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/**
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****************************************************************************************
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* @brief Init uart port (enable clock, reset, IO func map)
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*
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* @param[in] port uart port @see enum uart_port
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* @param[in] io_tx iopad of TXD @see enum pad_idx
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* @param[in] io_rx iopad of RXD @see enum pad_idx
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*
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****************************************************************************************
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*/
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void uart_init(uint8_t port, uint8_t io_tx, uint8_t io_rx);
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/**
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****************************************************************************************
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* @brief Config uart hardware flow control (IO func map, enable auto RTS)
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*
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* @param[in] port uart port @see enum uart_port
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* @param[in] io_rts iopad of RTS @see enum pad_idx
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* @param[in] io_cts iopad of CTS @see enum pad_idx
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*
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****************************************************************************************
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*/
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void uart_hwfc(uint8_t port, uint8_t io_rts, uint8_t io_cts);
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/**
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****************************************************************************************
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* @brief Config uart params, baudrate and ctrl bits
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*
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* @param[in] port index of port @see enum uart_port
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* @param[in] cfg_BRR baudrate divider @see BRR_DIV() or BRR_BAUD()
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* @param[in] cfg_LCR line-control bits @see LCR_BITS()
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*
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****************************************************************************************
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*/
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void uart_conf(uint8_t port, uint16_t cfg_BRR, uint16_t cfg_LCR);
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/**
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****************************************************************************************
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* @brief Config uart fifo level and receive timeout
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*
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* @param[in] port index of port @see enum uart_port
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* @param[in] fifo_ctl fifo control @see enum uart_fcr_bfs
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* @param[in] bits_rto rx timeout (unit in bits)
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* @param[in] intr_en interrupt enable @see enum uart_intr_bfs
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*
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****************************************************************************************
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*/
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void uart_fctl(uint8_t port, uint8_t fifo_ctl, uint16_t bits_rto, uint16_t intr_en);
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/**
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****************************************************************************************
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* @brief Config uart mode control
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*
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* @param[in] port index of port @see enum uart_port
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* @param[in] dma enable DMA or not
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*
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****************************************************************************************
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*/
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void uart_mctl(uint8_t port, uint8_t dma);
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/**
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****************************************************************************************
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* @brief Transmits one byte data through the UART port
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*
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* @param[in] port index of port @see enum uart_port
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* @param[in] ch the data transmited
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*
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****************************************************************************************
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*/
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void uart_putc(uint8_t port, uint8_t ch);
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/**
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****************************************************************************************
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* @brief Get the most recent received data by UART port
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*
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* @param[in] port index of port @see enum uart_port
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*
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* @return received data
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****************************************************************************************
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*/
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uint8_t uart_getc(uint8_t port);
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/**
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****************************************************************************************
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* @brief Wait uart transmit finish, in idle state
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*
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* @param[in] port index of port @see enum uart_port
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*
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****************************************************************************************
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*/
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void uart_wait(uint8_t port);
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/**
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****************************************************************************************
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* @brief Transmits bytes data through the UART port(Blocking Mode)
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*
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* @param[in] port index of port @see enum uart_port
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* @param[in] len data length
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* @param[in] data data pointer
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*
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****************************************************************************************
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*/
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void uart_send(uint8_t port, uint16_t len, const uint8_t *data);
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#endif //_UART_H_
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