136 lines
6.4 KiB
C
136 lines
6.4 KiB
C
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#ifndef _REG_SPIM_H_
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#define _REG_SPIM_H_
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#include "reg_base.h"
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//================================
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//BLOCK SPIM define
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#define SPIM_BASE ((uint32_t)0x40004000)
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#define SPIM_RX_DATA_ADDR_OFFSET 0x000
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#define SPIM_TX_DATA_ADDR_OFFSET 0x004
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#define SPIM_TXRX_BGN_ADDR_OFFSET 0x008
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#define SPIM_CTRL_ADDR_OFFSET 0x00c
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#define SPIM_STATUS_CLR_ADDR_OFFSET 0x010
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#define SPIM_STATUS_ADDR_OFFSET 0x014
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#define SPIM_DAT_LEN_ADDR_OFFSET 0x018
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//================================
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//BLOCK SPIM reg struct define
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typedef union //0x00c
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{
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struct
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{
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uint32_t SPIM_CRAT: 4; // bit[3:0] --- clock rate select,clk/2^(crat+1)
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// 0-11 is supported
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uint32_t SPIM_CPHA: 1; // bit4 --- clock phase bit
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// 0: sck sample data in first edge;
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// 1: sck sample data in second edge;
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uint32_t SPIM_CPOL: 1; // bit5 --- clock polarity bit
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// 0: sck is low in idle status;
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// 1: sck is high in idle status;
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uint32_t SPIM_TX_DMA_EN: 1; // bit6 ---
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// 0: TX work as mcu mode
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// 1: TX work as dma mode,after configure dma cfg,set txrx bgn to 1 to start the dma transission
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uint32_t SPIM_RX_DMA_EN: 1; // bit7 ---
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// 0: RX work as mcu mode
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// 1: RX work as dma mode,after configure dma cfg,set txrx bgn to 1 to start the dma transission
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uint32_t SPIM_INT_EN: 1; // bit8 --- interrupt enable bit
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uint32_t SPIM_TX_EN: 1; // bit9 --- transmit to SPI slave enable
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uint32_t SPIM_RX_EN: 1; // bit10--- receive from SPI slave enable
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uint32_t SPIM_MSB_FST: 1; // bit11---
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// 0: LSB first
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// 1: MSB first
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uint32_t RSV_END: 20; // bit[31:12]
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};
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uint32_t Word;
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} SPIM_CTRL_TypeDef; //0x00c
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//================================
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#define SPIM_SPIM_CRAT_LSB 0
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#define SPIM_SPIM_CRAT_WIDTH 4
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#define SPIM_SPIM_CPHA_POS 4
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#define SPIM_SPIM_CPOL_POS 5
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#define SPIM_SPIM_TX_DMA_EN_POS 6
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#define SPIM_SPIM_RX_DMA_EN_POS 7
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#define SPIM_SPIM_INT_EN_POS 8
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#define SPIM_SPIM_TX_EN_POS 9
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#define SPIM_SPIM_RX_EN_POS 10
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#define SPIM_SPIM_MSB_FST_POS 11
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#define SPIM_SPIM_RX_PH_POS 12
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//================================
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typedef union //0x010
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{
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struct
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{
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uint32_t SPIM_TXDAT_CLR: 1; // bit0 --- set 1 to clear spi TX fifo status and inner counter
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uint32_t SPIM_RXDAT_CLR: 1; // bit1 --- set 1 to clear spi RX fifo status and inner counter
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uint32_t SPIM_CLR_INTF: 1; // bit2 --- write 1 to clear intf status
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uint32_t RSV_END: 29; // bit[31:3]
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};
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uint32_t Word;
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} SPIM_STATUS_CLR_TypeDef; //0x010
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//================================
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#define SPIM_SPIM_TXDAT_CLR_POS 0
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#define SPIM_SPIM_RXDAT_CLR_POS 1
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#define SPIM_SPIM_CLR_INTF_POS 2
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//================================
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typedef union //0x014
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{
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struct
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{
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uint32_t SPIM_TX_FEMPTY: 1; // bit0 --- tx fifo empty
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uint32_t SPIM_TX_FFULL: 1; // bit1 --- tx fifo full
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uint32_t SPIM_TX_FNUM: 3; // bit[4:2] --- data number in tx fifo
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uint32_t SPIM_RX_FEMPTY: 1; // bit5 --- rx fifo empty
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uint32_t SPIM_RX_FFULL: 1; // bit6 --- rx fifo full
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uint32_t SPIM_RX_FNUM: 3; // bit[9:7] --- data length in rx fifo
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uint32_t SPIM_INTF: 1; // bit10 --- rx/tx interrupt flag
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uint32_t SPIM_BUSY: 1; // bit11 --- spim transfer busy signal
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// 0: spim idle
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// 1: spim busy,tx/rx is running
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uint32_t RSV_END: 20; // bit[31:12]
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};
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uint32_t Word;
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} SPIM_STATUS_TypeDef; //0x014
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//================================
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#define SPIM_SPIM_TX_FEMPTY_POS 0
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#define SPIM_SPIM_TX_FFULL_POS 1
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#define SPIM_SPIM_TX_FNUM_LSB 2
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#define SPIM_SPIM_TX_FNUM_WIDTH 3
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#define SPIM_SPIM_RX_FEMPTY_POS 5
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#define SPIM_SPIM_RX_FFULL_POS 6
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#define SPIM_SPIM_RX_FNUM_LSB 7
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#define SPIM_SPIM_RX_FNUM_WIDTH 3
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#define SPIM_SPIM_INTF_POS 10
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#define SPIM_SPIM_BUSY_POS 11
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//================================
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//================================
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//BLOCK SPIM top struct define
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typedef struct
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{
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__I uint32_t RX_DATA ; // 0x000,
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__O uint32_t TX_DATA ; // 0x004,
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__O uint32_t TXRX_BGN ; // 0x008,
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// used when dullplex mode or only RX mode
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__IO SPIM_CTRL_TypeDef CTRL ; // 0x00c,
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__O SPIM_STATUS_CLR_TypeDef STATUS_CLR ; // 0x010,
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__I SPIM_STATUS_TypeDef STATUS ; // 0x014,
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__IO uint32_t DAT_LEN ; // 0x018,
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// data length for RX in MCU or DMA mode
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// valid bit[15:0]
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} SPIM_TypeDef;
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#define SPIM (( SPIM_TypeDef *) SPIM_BASE)
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#endif
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