294 lines
11 KiB
C
294 lines
11 KiB
C
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/**
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****************************************************************************************
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*
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* @file sadc.h
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*
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* @brief Header file - SADC(ADC) Driver
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*
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****************************************************************************************
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*/
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#ifndef _SADC_H_
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#define _SADC_H_
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#include <stdint.h>
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/*
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* DEFINES
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****************************************************************************************
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*/
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enum sadc_chnl_set
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{
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// 0~4: Special Power Pads
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SADC_CH_VDD33 = 0, // VDD33/2
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SADC_CH_VBK = 1, // PAD_VBK
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SADC_CH_VDD12 = 2, // PAD_VDD12
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SADC_CH_PGAOUT = 3,
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SADC_CH_MICIN = 4,
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// 5~14: ADCIN0 ~ ADCIN9(Single ended channel)
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SADC_CH_AIN0 = 5, // PA00 or PA11
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SADC_CH_AIN1 = 6, // PA01 or PA12
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SADC_CH_AIN2 = 7, // PA02 or PA13
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SADC_CH_AIN3 = 8, // PA04
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SADC_CH_AIN4 = 9, // PA05 or PA14
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SADC_CH_AIN5 = 10, // PA06 or PA15
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SADC_CH_AIN6 = 11, // PA07 or PA16
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SADC_CH_AIN7 = 12, // PA08
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SADC_CH_AIN8 = 13, // PA09
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SADC_CH_AIN9 = 14, // PA10
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// 15: RF RSSI sample
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SADC_CH_RFRSV = 15, // RF.RF_RSV[3:0]
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};
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enum sadc_rf_rsv
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{
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SADC_RF_TEMP = 0x1, // 4'b0001
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SADC_RF_BANDGAP = 0x2, // 4'b0010
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SADC_RF_RSSI = 0x4, // 4'b0100
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SADC_RF_VDDIF = 0x8, // 4'b1000
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};
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enum sadc_ana_ctrl
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{
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// bit0 - SADC Enable
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SADC_EN_POS = 0,
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SADC_EN_BIT = (1 << SADC_EN_POS),
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// bit[2:1] - Vref Trim
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SADC_VREF_TRIM_LSB = 1,
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SADC_VREF_TRIM_1V2 = (0 << SADC_VREF_TRIM_LSB),
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SADC_VREF_TRIM_1V8 = (1 << SADC_VREF_TRIM_LSB),
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SADC_VREF_TRIM_2V4 = (2 << SADC_VREF_TRIM_LSB),
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SADC_VREF_TRIM_3V0 = (3 << SADC_VREF_TRIM_LSB),
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// bit[5:3] - ibsel cmp 15uA~105uA, step in 15uA
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SADC_IBSEL_CMP_LSB = 3,
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SADC_IBSEL_CMP_015UA = (0 << SADC_IBSEL_CMP_LSB),
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SADC_IBSEL_CMP_105UA = (7 << SADC_IBSEL_CMP_LSB),
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// bit[8:6] - ibsel vcm 15uA~105uA, step in 15uA
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SADC_IBSEL_VCM_LSB = 6,
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SADC_IBSEL_VCM_015UA = (0 << SADC_IBSEL_VCM_LSB),
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SADC_IBSEL_VCM_105UA = (7 << SADC_IBSEL_VCM_LSB),
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// bit[11:9] - ibsel Vref 15uA~105uA, step in 15uA
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SADC_IBSEL_VREF_LSB = 9,
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SADC_IBSEL_VREF_015UA = (0 << SADC_IBSEL_VREF_LSB),
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SADC_IBSEL_VREF_105UA = (7 << SADC_IBSEL_VREF_LSB),
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// bit[14:12] - ibsel buf 15uA~105uA, step in 15uA
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SADC_IBSEL_BUF_LSB = 12,
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SADC_IBSEL_BUF_015UA = (0 << SADC_IBSEL_BUF_LSB),
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SADC_IBSEL_BUF_105UA = (7 << SADC_IBSEL_BUF_LSB),
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// bit15 - SADC Vref gen from VBG or VDDA
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SADC_VREF_POS = 15,
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SADC_VREF_VDD = (0 << SADC_VREF_POS),
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SADC_VREF_VBG = (1 << SADC_VREF_POS),
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// bit[17:16] - SADC precision or range
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SADC_CALCAP_LSB = 16,
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SADC_CALCAP_PRECISION = (1 << SADC_CALCAP_LSB),
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SADC_CALCAP_RANGE = (3 << SADC_CALCAP_LSB),
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// bit[19:18] - SADC single ended tie to GND or VREF
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SADC_CALOS_POS = 18,
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SADC_CALOS_GND = (0 << SADC_CALOS_POS),
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SADC_CALOS_VREF = (1 << SADC_CALOS_POS),
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// bit20 - SADC bypass input buffer
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SADC_INBUF_BYPSS_POS = 20,
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SADC_INBUF_BYPSS_BIT = (1 << SADC_INBUF_BYPSS_POS),
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};
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#define SADC_IBSEL_CMP(sel) ((sel) << SADC_IBSEL_CMP_LSB)
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#define SADC_IBSEL_VCM(sel) ((sel) << SADC_IBSEL_VCM_LSB)
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#define SADC_IBSEL_VREF(sel) ((sel) << SADC_IBSEL_VREF_LSB)
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#define SADC_IBSEL_BUF(sel) ((sel) << SADC_IBSEL_BUF_LSB)
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#define SADC_ANA_DFLT (SADC_VREF_VBG | SADC_CALCAP_PRECISION | SADC_IBSEL_BUF(3) | SADC_IBSEL_VREF(3) \
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| SADC_IBSEL_VCM(3) | SADC_IBSEL_CMP(3) | SADC_VREF_TRIM_2V4 | SADC_EN_BIT)
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#define SADC_ANA_VREF_1V2 (SADC_VREF_VBG | SADC_CALCAP_PRECISION | SADC_IBSEL_BUF(3) | SADC_IBSEL_VREF(3) \
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| SADC_IBSEL_VCM(3) | SADC_IBSEL_CMP(3) | SADC_VREF_TRIM_1V2 | SADC_EN_BIT)
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#define SADC_ANA_VREF_2V4 (SADC_VREF_VBG | SADC_CALCAP_PRECISION | SADC_IBSEL_BUF(3) | SADC_IBSEL_VREF(3) \
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| SADC_IBSEL_VCM(3) | SADC_IBSEL_CMP(3) | SADC_VREF_TRIM_2V4 | SADC_EN_BIT)
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#define SADC_ANA_VREF_VDD (SADC_VREF_VDD | SADC_CALCAP_PRECISION | SADC_IBSEL_BUF(3) | SADC_IBSEL_VREF(3) \
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| SADC_IBSEL_VCM(3) | SADC_IBSEL_CMP(3) | SADC_EN_BIT)
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enum sadc_mic_sel
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{
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// bit0 - Analog microphone connect mode
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SADC_MIC_MODE_POS = 0,
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SADC_MIC_MODE_CAP = (0 << SADC_MIC_MODE_POS),
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SADC_MIC_MODE_NO_CAP = (1 << SADC_MIC_MODE_POS),
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// bit1 - Micbias powerdown signal
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SADC_MIC_PWD_POS = 1,
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SADC_MIC_PWD_BIT = (1 << SADC_MIC_PWD_POS),
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// bit[8:2] - Micbias output voltage trimming signal
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SADC_MIC_TRIM_LSB = 2,
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SADC_MIC_TRIM_MSK = (0x7F << SADC_MIC_TRIM_LSB),
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// bit9 - Micbias Internal voltage reference(0:750mV, 1:1.5V)
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SADC_MIC_VREF_POS = 9,
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SADC_MIC_VREF_750MV = (0 << SADC_MIC_VREF_POS),
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SADC_MIC_VREF_1V5 = (1 << SADC_MIC_VREF_POS),
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// bit[11:10] - pga voltage trimming signal
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SADC_PGA_BIAS_LSB = 10,
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SADC_PGA_BIAS_MSK = (0x03 << SADC_PGA_BIAS_LSB),
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// bit12 - pga enable signal
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SADC_PGA_EN_POS = 12,
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SADC_PGA_EN_BIT = (1 << SADC_PGA_EN_POS),
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// bit[17:13] - pga voltage trimming signal
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SADC_PGA_VOL_LSB = 13,
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SADC_PGA_VOL_MSK = (0x1F << SADC_PGA_VOL_LSB),
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// bit18 - pga Internal voltage reference(0:750mV, 1:1.5V)
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SADC_PGA_VREF_POS = 18,
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SADC_PGA_VREF_750MV = (0 << SADC_PGA_VREF_POS),
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SADC_PGA_VREF_1V5 = (1 << SADC_PGA_VREF_POS),
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};
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#define SADC_MIC_TRIM(val) ((val) << SADC_MIC_TRIM_LSB)
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#define SADC_PGA_BIAS(val) ((val) << SADC_PGA_BIAS_LSB)
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#define SADC_PGA_VOL(val) ((val) << SADC_PGA_VOL_LSB)
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// .MIC_PD=0, .MIC_VREF_SEL=1, .PGA_BIAS_SEL=1, .PGA_EN=1
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#define SADC_MIC_DFLT (SADC_PGA_VOL(0x1B) | SADC_PGA_BIAS(1) | SADC_MIC_TRIM(0x40) \
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| SADC_PGA_EN_BIT | SADC_PGA_VREF_1V5 | SADC_MIC_VREF_1V5) // 0x36502->0x77700
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enum sadc_ctrl_bfs
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{
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// bit0 - start of conversion
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SADC_CR_SOC_POS = 0,
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SADC_CR_SOC_BIT = (1 << SADC_CR_SOC_POS),
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// bit1 - calibration mode
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SADC_CR_CALIB_POS = 1,
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SADC_CR_CALIB_BIT = (1 << SADC_CR_CALIB_POS),
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// bit2 - conversion mode(0-single, 1-continue)
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SADC_CR_CONV_MODE_POS = 2,
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SADC_CR_CONV_MODE_BIT = (1 << SADC_CR_CONV_MODE_POS),
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SADC_CR_CONV_SINGLE = (0 << SADC_CR_CONV_MODE_POS),
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SADC_CR_CONV_CONTINUE = (1 << SADC_CR_CONV_MODE_POS),
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// bit3 - DMA enable
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SADC_CR_DMAEN_POS = 3,
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SADC_CR_DMAEN_BIT = (1 << SADC_CR_DMAEN_POS),
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// bit4 - conversion at clk phase(0-negedge, 1-posedge)
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SADC_CR_CLKPH_POS = 4,
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SADC_CR_CLKPH_NEGEDGE = (0 << SADC_CR_CLKPH_POS),
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SADC_CR_CLKPH_POSEDGE = (1 << SADC_CR_CLKPH_POS),
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// bit[6:5] - Sample mode
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SADC_CR_SAMP_MODE_LSB = 5,
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SADC_CR_SAMP_MODE_MSK = (0x03 << SADC_CR_SAMP_MODE_LSB),
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SADC_CR_SAMP_SOFT = (0 << SADC_CR_SAMP_MODE_LSB), // software mode(normal mode)
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SADC_CR_SAMP_RSSI = (1 << SADC_CR_SAMP_MODE_LSB), // RSSI sample mode( ADC controlled by BB)
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SADC_CR_SAMP_PCM = (2 << SADC_CR_SAMP_MODE_LSB), // sample vioce data, must enable DMA
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SADC_CR_SAMP_ADTMR = (3 << SADC_CR_SAMP_MODE_LSB), // SOC is from ADTIM adctrg
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// bit7 - write as 1 to stop decimation filter
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SADC_CR_PCMEND_POS = 7,
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SADC_CR_PCMEND_BIT = (1 << SADC_CR_PCMEND_POS),
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// bit[13:8] - delay time from rssi_req to SADC sample RSSI
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SADC_CR_RSSI_DLY_LSB = 8,
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SADC_CR_RSSI_DLY_MSK = (0x3F << SADC_CR_RSSI_DLY_LSB),
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// bit14 - DBG enable, configed as SADC analog IP
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SADC_CR_DBGEN_POS = 14,
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SADC_CR_DBGEN_BIT = (1 << SADC_CR_DBGEN_POS),
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// bit[19:16] - decimation filter high pass filter coef
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SADC_CR_HPF_COEF_LSB = 16,
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SADC_CR_HPF_COEF_MSK = (0x0F << SADC_CR_HPF_COEF_LSB),
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// bit[29:20] - adc function clock = hclk / (sadc_aux_clk_div + 1)
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SADC_CR_CLK_DIV_LSB = 20,
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SADC_CR_CLK_DIV_MSK = (0x3FF << SADC_CR_CLK_DIV_LSB),
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};
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#define SADC_CR_HPF(coef) ((coef) << SADC_CR_HPF_COEF_LSB)
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#define SADC_CR_CLK(div) ((div) << SADC_CR_CLK_DIV_LSB)
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#define SADC_CR_DFLT (SADC_CR_CLK(3) | SADC_CR_HPF(11) | SADC_CR_CLKPH_POSEDGE \
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| SADC_CR_SAMP_SOFT | SADC_CR_CONV_SINGLE) // 0x3B0010
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/*
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* FUNCTION DECLARATION
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****************************************************************************************
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*/
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/**
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****************************************************************************************
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* @brief Init SADC Module.
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*
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* @param[in] ana_ctrl Bits field of value @see enum sadc_ana_ctrl.
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****************************************************************************************
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*/
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void sadc_init(uint32_t ana_ctrl);
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/**
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****************************************************************************************
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* @brief Config SADC Module.
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*
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* @param[in] ctrl Bits field of value @see enum sadc_ctrl_bfs.
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****************************************************************************************
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*/
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void sadc_conf(uint32_t ctrl);
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/**
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****************************************************************************************
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* @brief SADC read data.
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*
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* @param[in] chset Bits field of value @see enum sadc_chnl_set.
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* @param[in] times Number of times sadc read.
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*
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* @return Multiple(times) averages.
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****************************************************************************************
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*/
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uint16_t sadc_read(uint8_t chset, uint16_t times);
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/**
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****************************************************************************************
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* @brief Config SADC Support DMA.
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*
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* @param[in] sw_auto SADC auto chnl.
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* @param[in] ch_ctrl Bits field of value @see enum sadc_chnl_set.
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****************************************************************************************
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*/
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void sadc_dma(uint8_t sw_auto, uint32_t ch_ctrl);
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/**
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****************************************************************************************
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* @brief Config SADC Support PCM.
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*
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* @param[in] mic_sel Bits field of value @see enum sadc_mic_sel.
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****************************************************************************************
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*/
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void sadc_pcm(uint32_t mic_sel);
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/**
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****************************************************************************************
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* @brief Config SADC Support ATMR.
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*
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* @param[in] sw_auto SADC auto chnl.
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* @param[in] ch_ctrl Bits field of value @see enum sadc_chnl_set.
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****************************************************************************************
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*/
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void sadc_atmr(uint8_t sw_auto, uint32_t ch_ctrl);
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/**
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****************************************************************************************
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* @brief Random Number Generated by SADC.
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*
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* @return Random Number.
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****************************************************************************************
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*/
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uint32_t sadc_rand_num(void);
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#endif // _SADC_H_
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