106 lines
5.1 KiB
C
106 lines
5.1 KiB
C
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#ifndef _REG_BTMR_H_
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#define _REG_BTMR_H_
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#include "reg_base.h"
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//================================
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//BLOCK BTMR define
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#define BTMR_BASE ((uint32_t)0x40020000)
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#define BTMR_CR1_ADDR_OFFSET 0x000
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#define BTMR_CR2_ADDR_OFFSET 0x004
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#define BTMR_IER_ADDR_OFFSET 0x00c
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#define BTMR_IDR_ADDR_OFFSET 0x010
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#define BTMR_IVS_ADDR_OFFSET 0x014
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#define BTMR_RIF_ADDR_OFFSET 0x018
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#define BTMR_IFM_ADDR_OFFSET 0x01c
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#define BTMR_ICR_ADDR_OFFSET 0x020
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#define BTMR_EGR_ADDR_OFFSET 0x024
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#define BTMR_CNT_ADDR_OFFSET 0x034
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#define BTMR_PSC_ADDR_OFFSET 0x038
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#define BTMR_ARR_ADDR_OFFSET 0x03c
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#define BTMR_DMAEN_ADDR_OFFSET 0x058
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//================================
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//BLOCK BTMR reg struct define
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typedef union //0x000
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{
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struct
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{
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uint32_t CEN: 1; // bit0 --- counter enable
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uint32_t UDIS: 1; // bit1 --- update disable
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uint32_t URS: 1; // bit2 --- update request source
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uint32_t OPM: 1; // bit3 --- one plus mode
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uint32_t RSV_NOUSE1: 3; // bit[6:4]-Ignore me
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uint32_t ARPE: 1; // bit7 --- auto reload preload enable
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uint32_t RSV_END: 24; // bit[31:8]
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};
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uint32_t Word;
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} BTMR_CR1_TypeDef; //0x000
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//================================
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#define BTMR_CEN_POS 0
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#define BTMR_UDIS_POS 1
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#define BTMR_URS_POS 2
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#define BTMR_OPM_POS 3
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#define BTMR_ARPE_POS 7
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//================================
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typedef union //0x004
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{
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struct
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{
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uint32_t RSV_NOUSE1: 4; // bit[3:0] --- Ignore me
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uint32_t MMS: 3; // bit[6:4] --- master mode select=
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uint32_t RSV_END: 25; // bit[31:7]
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};
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uint32_t Word;
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} BTMR_CR2_TypeDef; //0x004
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//================================
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#define BTMR_MMS_LSB 4
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#define BTMR_MMS_WIDTH 3
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//================================
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//================================
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//BLOCK BTMR top struct define
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typedef struct
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{
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__IO BTMR_CR1_TypeDef CR1 ; // 0x000,
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// control register 1
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__IO BTMR_CR2_TypeDef CR2 ; // 0x004,
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// control register 2
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__I uint32_t RSV0[1] ;
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__O uint32_t IER ; // 0x00c,
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// interrupt enable register
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__O uint32_t IDR ; // 0x010,
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// interrupt disable register
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__I uint32_t IVS ; // 0x014,
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// interrupt vaild status register
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__I uint32_t RIF ; // 0x018,
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// interrupt raw flag register
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__I uint32_t IFM ; // 0x01c,
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// interrupt masked flag register
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__O uint32_t ICR ; // 0x020,
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// interrupt clear status register
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__IO uint32_t EGR ; // 0x024,
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// event generation register
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__I uint32_t RSV1[3] ;
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__IO uint32_t CNT ; // 0x034,
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// timer counter
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__IO uint32_t PSC ; // 0x038,
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// prescaler
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__IO uint32_t ARR ; // 0x03c,
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// auto-reload register
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__I uint32_t RSV2[6] ;
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__IO uint32_t DMAEN ; // 0x058,
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// dma trigger event enable
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} BTMR_TypeDef;
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#define BTMR (( BTMR_TypeDef *) BTMR_BASE)
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#endif
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