163 lines
8.5 KiB
C
163 lines
8.5 KiB
C
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#ifndef _REG_SPIS_H_
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#define _REG_SPIS_H_
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#include "reg_base.h"
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//================================
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//BLOCK SPIS define
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#define SPIS_BASE ((uint32_t)0x40005000)
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#define SPIS_CTRL_ADDR_OFFSET 0x000
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#define SPIS_STATUS_ADDR_OFFSET 0x004
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#define SPIS_INFO_CLR_ADDR_OFFSET 0x008
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#define SPIS_TX_DAT_ADDR_OFFSET 0x00c
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#define SPIS_RX_DAT_ADDR_OFFSET 0x010
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//================================
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//BLOCK SPIS reg struct define
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typedef union //0x000
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{
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struct
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{
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uint32_t SPIS_LSBFIRST: 1; // bit0 ---
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// 0: MSB first for SPIS TX/RX;
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// 1: LSB first for SPIS TX/RX;
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uint32_t SPIS_CPOL: 1; // bit1 --- spi clock polarity control bit when SPIS is IDLE(cs is 1);
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// 0: sample the data at the first clock edge
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// 1: sample the data at the second clock edge
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uint32_t SPIS_CPHA: 1; // bit2 --- clock phase used for sample data
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// 0: sample the data at the first clock edge
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// 1: sample the data at the second clock edge
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uint32_t SPIS_RX_EN: 1; // bit3 --- spis rx control signal
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// default is enable
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// 0: spis RX disable
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// 1: spis RX enable
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// SPIS RX enable only when both spis en and spis rx en set as 1
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uint32_t SPIS_RXINT_EN: 1; // bit4 ---
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// 0: spis_rxint interrupt disable
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// 1: spis_rxint interrupt enable
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uint32_t SPIS_TX_DMA_MODE: 1; // bit5 --- SPIS TX operation mode control signal
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// 1: DMA mode
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// 0: MCU mode
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uint32_t SPIS_RX_DMA_MODE: 1; // bit6 --- SPIS RX operation mode control signal
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// 1: DMA mode
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// 0: MCU mode
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uint32_t SPIS_EN: 1; // bit7 ---
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// 0: SPIS work disable
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// 1: spis work enable
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// [Note:the spis lsfirst,spis spol and spis spha can be configured only when spis en is 0]
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uint32_t SPIS_OT_WIN: 8; // bit[15:8] --- config overtime window
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// unit : bit width time
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uint32_t SPIS_OT_EN: 1; // bit16 --- SPIS overtime enable
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uint32_t SPIS_OTINT_EN: 1; // bit17
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uint32_t RSV_END: 14; // bit[31:18]
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};
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uint32_t Word;
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} SPIS_CTRL_TypeDef; //0x000
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//================================
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#define SPIS_SPIS_LSBFIRST_POS 0
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#define SPIS_SPIS_CPOL_POS 1
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#define SPIS_SPIS_CPHA_POS 2
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#define SPIS_SPIS_RX_EN_POS 3
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#define SPIS_SPIS_RXINT_EN_POS 4
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#define SPIS_SPIS_TX_DMA_MODE_POS 5
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#define SPIS_SPIS_RX_DMA_MODE_POS 6
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#define SPIS_SPIS_EN_POS 7
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#define SPIS_SPIS_OT_WIN_LSB 8
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#define SPIS_SPIS_OT_WIN_WIDTH 8
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#define SPIS_SPIS_OT_EN_POS 16
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#define SPIS_SPIS_OTINT_EN_POS 17
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//================================
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typedef union //0x004
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{
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struct
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{
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uint32_t SPIS_RXFIFO_EMPTY: 1; // bit0 ---
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// 0: spis_rxfifo is not empty
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// 1: spis_rxfifo is empty
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uint32_t SPIS_RXFIFO_FULL: 1; // bit1 ---
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// 0: spis_rxfifo is not full
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// 1: spis_rxfifo is full
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uint32_t SPIS_RXFIFO_NUM: 3; // bit[4:2] --- the SPIS RX data number in rxfifo
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uint32_t RSV_NOUSE1: 1; // bit5 --- Ignore me
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uint32_t SPIS_RX_OVERRUN: 1; // bit6 --- SPIS rxfifo overrun error signal
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// 0: cleared by spis rx overrun clr
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// 1: rxfifo overrun error
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uint32_t SPIS_CS: 1; // bit7 --- the signal pin SPIS_CS
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// 0: SPIS is selected
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// 1: SPIS is not selected
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uint32_t SPIS_TXFIFO_EMPTY: 1; // bit8 ---
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// 0: spis_txfifo is not empty
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// 1: spis_txfifo is empty
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uint32_t SPIS_TXFIFO_FULL: 1; // bit9 ---
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// 0: spis_txfifo is not full
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// 1: spis_txfifo is full
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// [Note:When txfifo is not full,MCU can write tx dat reg
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uint32_t SPIS_TXFIFO_NUM: 3; // bit[12:10] --- the SPIS TX data number in txfifo
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uint32_t RSV_NOUSE2: 3; // bit[15:13] --- Ignore me
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uint32_t SPIS_RXINT_ST: 1; // bit16 --- when SPIS RX 1 byte,spis_rxint is 1
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// cleared by spis_rxint_clr
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uint32_t SPIS_OTINT_ST: 1; // bit17 --- set as 1 when SPIS overtime event happen
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uint32_t RSV_END: 14; // bit[31:18]
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};
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uint32_t Word;
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} SPIS_STATUS_TypeDef; //0x004
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//================================
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#define SPIS_SPIS_RXFIFO_EMPTY_POS 0
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#define SPIS_SPIS_RXFIFO_FULL_POS 1
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#define SPIS_SPIS_RXFIFO_NUM_LSB 2
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#define SPIS_SPIS_RXFIFO_NUM_WIDTH 3
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#define SPIS_SPIS_RX_OVERRUN_POS 6
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#define SPIS_SPIS_CS_POS 7
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#define SPIS_SPIS_TXFIFO_EMPTY_POS 8
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#define SPIS_SPIS_TXFIFO_FULL_POS 9
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#define SPIS_SPIS_TXFIFO_NUM_LSB 10
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#define SPIS_SPIS_TXFIFO_NUM_WIDTH 3
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#define SPIS_SPIS_RXINT_ST_POS 16
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#define SPIS_SPIS_OTINT_ST_POS 17
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//================================
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typedef union //0x008
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{
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struct
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{
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uint32_t SPIS_RX_OVERRUN_CLR: 1; // bit0 --- use to clear spis_rx_overrun
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uint32_t SPIS_TXDAT_CLR: 1; // bit1 --- use to clear SPIS txfifo point and data reg
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uint32_t SPIS_RXDAT_CLR: 1; // bit2 --- use to clear SPIS rxfifo point and data reg
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uint32_t SPIS_RXINT_CLR: 1; // bit3 --- use clear spis_rxint
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uint32_t SPIS_OTINT_CLR: 1; // bit4
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uint32_t RSV_END: 27; // bit[31:5]
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};
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uint32_t Word;
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} SPIS_INFO_CLR_TypeDef; //0x008
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//================================
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#define SPIS_SPIS_RX_OVERRUN_CLR_POS 0
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#define SPIS_SPIS_TXDAT_CLR_POS 1
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#define SPIS_SPIS_RXDAT_CLR_POS 2
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#define SPIS_SPIS_RXINT_CLR_POS 3
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#define SPIS_SPIS_OTINT_CLR_POS 4
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//================================
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//================================
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//BLOCK SPIS top struct define
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typedef struct
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{
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__IO SPIS_CTRL_TypeDef CTRL ; // 0x000,
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__I SPIS_STATUS_TypeDef STATUS ; // 0x004,
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__O SPIS_INFO_CLR_TypeDef INFO_CLR ; // 0x008,
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__O uint32_t TX_DAT ; // 0x00c,
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__I uint32_t RX_DAT ; // 0x010,
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} SPIS_TypeDef;
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#define SPIS (( SPIS_TypeDef *) SPIS_BASE)
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#endif
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