240 lines
14 KiB
C
240 lines
14 KiB
C
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#ifndef _REG_SYSCFG_H_
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#define _REG_SYSCFG_H_
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#include "reg_base.h"
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//================================
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//BLOCK SYSCFG define
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#define SYSCFG_BASE ((uint32_t)0x40001000)
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#define SYSCFG_BB_PMU_ENABLE_ADDR_OFFSET 0x000
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#define SYSCFG_AHB_MATRIX_PRIORITY_ADDR_OFFSET 0x004
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#define SYSCFG_DBG_CTRL_ADDR_OFFSET 0x008
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#define SYSCFG_USB_CTRL_ADDR_OFFSET 0x00c
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#define SYSCFG_ROM_CTRL_ADDR_OFFSET 0x010
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#define SYSCFG_SRAM_CTRL_ADDR_OFFSET 0x014
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#define SYSCFG_ROM_SIGNATURE_TARGET_ADDR_OFFSET 0x018
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#define SYSCFG_BIST_MODE_ADDR_OFFSET 0x01c
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#define SYSCFG_BIST_STATUS_ADDR_OFFSET 0x020
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#define SYSCFG_BIST_STATUS_CLR_ADDR_OFFSET 0x024
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#define SYSCFG_ROM_SIGNATURE_RPT_ADDR_OFFSET 0x028
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#define SYSCFG_CACHSRAM_CFG_ADDR_OFFSET 0x02c
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#define SYSCFG_EM_BASE_CFG_ADDR_OFFSET 0x030
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#define SYSCFG_CACHE_ACCESS_CNT_ADDR_OFFSET 0x034
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#define SYSCFG_CACHE_HIT_CNT_ADDR_OFFSET 0x038
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#define SYSCFG_ACC_CCR_BUSY_ADDR_OFFSET 0x03c
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#define SYSCFG_MFV_ARRAY_D_ADDR_OFFSET 0x040
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#define SYSCFG_SYS_BACKUP0_ADDR_OFFSET 0x044
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//================================
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//BLOCK SYSCFG reg struct define
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typedef union //0x008
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{
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struct
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{
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uint32_t SYS_DEBUG_SEL: 2; // bit[1:0] ---
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// 2'b00: rf_debug port enable
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// 2'b01: BB debug port enable
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// 2'b10: MODEM debug port enable
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// 2'b11: USB debug port enable
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uint32_t RF_EXT_EN: 1; // bit2 --- chip set as RF IP block
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// 0: rf reg is controlled by on chip logic;
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// 1: rf reg is controlled by external through SPI interface
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uint32_t RF_SPI_EN: 1; // bit3 ---
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// 0: RF reg is direct controlled by APB interface
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// 1: RF reg is controlled by SPI interface
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// note
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// {rf_ext_en,rf_spi_en}
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// 00: rf reg is controlled by on chip APB interface
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// 01: rf reg is controlled by BB througth SPI interface
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// 11: rf reg is controlled by external Chip through SPI interface
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// 10: forbidden
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uint32_t IWDT_DEBUG: 1; // bit4
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uint32_t USB_DBG_SEL: 2; // bit[6:5]
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uint32_t RSV_END: 25; // bit[31:7]
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};
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uint32_t Word;
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} SYSCFG_DBG_CTRL_TypeDef; //0x008
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//================================
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#define SYSCFG_SYS_DEBUG_SEL_LSB 0
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#define SYSCFG_SYS_DEBUG_SEL_WIDTH 2
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#define SYSCFG_RF_EXT_EN_POS 2
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#define SYSCFG_RF_SPI_EN_POS 3
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#define SYSCFG_IWDT_DEBUG_POS 4
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#define SYSCFG_USB_DBG_SEL_LSB 5
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#define SYSCFG_USB_DBG_SEL_WIDTH 2
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//================================
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typedef union //0x00c
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{
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struct
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{
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uint32_t USB_SOF_INT_EN: 1; // bit0 --- when is 1, USB SOF signal can be used as interrupt
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uint32_t USB_PHY_MOD: 1; // bit1 ---
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// 1: the chip is set as USB PHY
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uint32_t DIG_USB_PU: 2; // bit[3:2] --- set as 1 when USB function enable
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// when is 1, enable pullup 1.5K for DP
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uint32_t DIG_USB_RXEN: 1; // bit4
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uint32_t RSV_NOUSE1: 3; // bit[7:5] --- Ignore me
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uint32_t USB_NRSTO: 1; // bit8 --- when is 1, USB is exit reset
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uint32_t USB_SUSPEND: 1; // bit9
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uint32_t RSV_END: 22; // bit[31:10]
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};
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uint32_t Word;
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} SYSCFG_USB_CTRL_TypeDef; //0x00c
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//================================
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#define SYSCFG_USB_SOF_INT_EN_POS 0
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#define SYSCFG_USB_PHY_MOD_POS 1
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#define SYSCFG_DIG_USB_PU_LSB 2
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#define SYSCFG_DIG_USB_PU_WIDTH 2
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#define SYSCFG_DIG_USB_RXEN_POS 4
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#define SYSCFG_USB_NRSTO_POS 8
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#define SYSCFG_USB_SUSPEND_POS 9
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//================================
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typedef union //0x010
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{
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struct
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{
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uint32_t ROM_RDMG: 4; // bit[3:0]
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uint32_t ROM_RDMG_EN: 1; // bit4
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uint32_t MEM_SCAN_IN: 1; // bit5
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uint32_t RSV_NOUSE1: 2; // bit[7:6] --- Ignore me
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uint32_t MDM_RDMG: 3; // bit[10:8]
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uint32_t MDM_RDMG_EN: 1; // bit11
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uint32_t RSV_END: 20; // bit[31:12]
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};
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uint32_t Word;
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} SYSCFG_ROM_CTRL_TypeDef; //0x010
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//================================
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#define SYSCFG_ROM_RDMG_LSB 0
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#define SYSCFG_ROM_RDMG_WIDTH 4
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#define SYSCFG_ROM_RDMG_EN_POS 4
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#define SYSCFG_MEM_SCAN_IN_POS 5
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#define SYSCFG_MDM_RDMG_LSB 8
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#define SYSCFG_MDM_RDMG_WIDTH 3
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#define SYSCFG_MDM_RDMG_EN_POS 11
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//================================
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typedef union //0x014
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{
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struct
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{
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uint32_t TAG_RDMG: 4; // bit[3:0]
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uint32_t CACHE_RDMG: 4; // bit[7:4]
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uint32_t EM_RDMG: 4; // bit[11:8]
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uint32_t SADCMEM_RDMG: 4; // bit[15:12]
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uint32_t USBMEM_RDMG: 4; // bit[19:16]
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uint32_t DSRAM_RDMG: 3; // bit[22:20]
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uint32_t RSV_NOUSE1: 1; // bit23 --- Ignore me
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uint32_t TAG_RDMG_EN: 1; // bit24
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uint32_t CACHE_RDMG_EN: 1; // bit25
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uint32_t EM_RDMG_EN: 1; // bit26
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uint32_t SADCMEM_RDMG_EN: 1; // bit27
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uint32_t USBMEM_RDMG_EN: 1; // bit28
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uint32_t DSRAM_RDMG_EN: 1; // bit29
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uint32_t RSV_END: 2; // bit[31:30]
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};
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uint32_t Word;
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} SYSCFG_SRAM_CTRL_TypeDef; //0x014
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//================================
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#define SYSCFG_TAG_RDMG_LSB 0
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#define SYSCFG_TAG_RDMG_WIDTH 4
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#define SYSCFG_CACHE_RDMG_LSB 4
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#define SYSCFG_CACHE_RDMG_WIDTH 4
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#define SYSCFG_EM_RDMG_LSB 8
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#define SYSCFG_EM_RDMG_WIDTH 4
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#define SYSCFG_SADCMEM_RDMG_LSB 12
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#define SYSCFG_SADCMEM_RDMG_WIDTH 4
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#define SYSCFG_USBMEM_RDMG_LSB 16
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#define SYSCFG_USBMEM_RDMG_WIDTH 4
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#define SYSCFG_DSRAM_RDMG_LSB 20
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#define SYSCFG_DSRAM_RDMG_WIDTH 3
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#define SYSCFG_TAG_RDMG_EN_POS 24
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#define SYSCFG_CACHE_RDMG_EN_POS 25
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#define SYSCFG_EM_RDMG_EN_POS 26
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#define SYSCFG_SADCMEM_RDMG_EN_POS 27
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#define SYSCFG_USBMEM_RDMG_EN_POS 28
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#define SYSCFG_DSRAM_RDMG_EN_POS 29
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//================================
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//================================
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//BLOCK SYSCFG top struct define
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typedef struct
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{
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__IO uint32_t BB_PMU_ENABLE ; // 0x000,
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__IO uint32_t AHB_MATRIX_PRIORITY ; // 0x004,
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__IO SYSCFG_DBG_CTRL_TypeDef DBG_CTRL ; // 0x008,
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__IO SYSCFG_USB_CTRL_TypeDef USB_CTRL ; // 0x00c,
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__IO SYSCFG_ROM_CTRL_TypeDef ROM_CTRL ; // 0x010,
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__IO SYSCFG_SRAM_CTRL_TypeDef SRAM_CTRL ; // 0x014,
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__IO uint32_t ROM_SIGNATURE_TARGET; // 0x018,
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// set rom_target_signature value before bist_mode as 1
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__IO uint32_t BIST_MODE ; // 0x01c,
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// all sram and rom bist start
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// note: bist follow
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// mode 1 : get report from GPIO
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// 1) : config GPIO for glb_bist_done and glb_bist_fail
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// 2) : set rom_signature_target value
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// 3) : set bist_mode as 1
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// 4) : wait a fixed time
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// 5) : check the glb_bist_done and glb_bist_fail state through GPIO
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//
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// mode 2 : get report from bist_statues
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// 1) : set rom_signature_target value
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// 2) : set bist_mode as 1
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// 3) : wait a fixed time
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// 4) : reset chip, and reconnect chip through UART
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// 5) : check the glb_bist_done and glb_bist_fail state through bist_status[1:0]
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// option step 6) : set bist_status_clr as 1 for clear status
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__I uint32_t BIST_STATUS ; // 0x020,
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// [0] global bist done
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// [1] global bist fail
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// [2] em_bist_done
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// [3] sram_bist_done
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// [4] sadcmem_bist_done
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// [5] mdm_bist_done
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// [6] rom_bist_done
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// [7] em_bist_fail
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// [8] sram_bist_fail
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// [9] sadcmem_bist_fail
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// [10] mdmmem_bist_fail
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// [11] rom_bist_fail
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__O uint32_t BIST_STATUS_CLR ; // 0x024,
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__I uint32_t ROM_SIGNATURE_RPT ; // 0x028,
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// rom signature report, just use for debug
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__IO uint32_t CACHSRAM_CFG ; // 0x02c,
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// 0: the 4KB sram use as CACHE
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// 1: the 4KB sram use as DATA SRAM: 0x2000_6000 ~ 0x2000_6FFF
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__IO uint32_t EM_BASE_CFG ; // 0x030,
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// 1KB step
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// 0: BB EM base addr: 0x2000_8000, EM size : 8KB
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// 1: BB EM base addr: 0x2000_8400, EM size : 7KB
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// 2: BB EM base addr: 0x2000_8800, EM size : 6KB
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// 3: BB EM base addr: 0x2000_8c00, EM size : 5KB
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// 4: BB EM base addr: 0x2000_9000, EM size : 4KB
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// 5: BB EM base addr: 0x2000_9400, EM size : 3KB
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// 6: BB EM base addr: 0x2000_9800, EM size : 2KB
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// 7: BB EM base addr: 0x2000_9c00, EM size : 1KB
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__I uint32_t CACHE_ACCESS_CNT ; // 0x034,
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__I uint32_t CACHE_HIT_CNT ; // 0x038,
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__I uint32_t ACC_CCR_BUSY ; // 0x03c,
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// cache status
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__I uint32_t MFV_ARRAY_D ; // 0x040,
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__IO uint32_t SYS_BACKUP0 ; // 0x044,
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// only reset by core por12_core_stb
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} SYSCFG_TypeDef;
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#define SYSCFG (( SYSCFG_TypeDef *) SYSCFG_BASE)
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#endif
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