134 lines
6.9 KiB
C
134 lines
6.9 KiB
C
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#ifndef _B6X_H_
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#define _B6X_H_
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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typedef enum IRQn
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{
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/****** Cortex-M0 Processor Exceptions Numbers *************************************************/
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NMI_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
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/****** Cortex-M0 specific Interrupt Numbers **********************************************/
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EXTI_IRQn = 0, /* 0 | EXTI Interrupt */
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IWDT_IRQn = 1, /* 1 | IWDT Interrupt */
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BLE_IRQn = 2, /* 2 | BLE Interrupt */
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DMAC_IRQn = 3, /* 3 | DMAC Interrupt */
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BB_LP_IRQn = 4, /* 4 | BB WAKEUP Interrupt */
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BTMR_IRQn = 5, /* 5 | BTMR Interrupt */
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CTMR_IRQn = 6, /* 6 | CTMR Interrupt */
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ATMR_IRQn = 7, /* 7 | ATMR Interrupt */
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RTC_IRQn = 8, /* 8 | RTC Interrupt */
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I2C_IRQn = 9, /* 9 | I2C Interrupt */
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SPIM_IRQn = 10, /* 10 | SPIM Interrupt */
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SPIS_IRQn = 11, /* 11 | SPIS Interrupt */
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UART1_IRQn = 12, /* 12 | UART1 Interrupt */
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UART2_IRQn = 13, /* 13 | UART2 Interrupt */
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AON_PMU_IRQn = 14, /* 14 | AON_PMU Interrupt */
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LVD33_IRQn = 15, /* 15 | LVD33 Interrupt */
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BOD12_IRQn = 16, /* 16 | BOD12 Interrupt */
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USB_IRQn = 17, /* 17 | USB Interrupt */
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USB_SOF_IRQn = 18, /* 18 | USB_SOF Interrupt */
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FSHC_IRQn = 19, /* 19 | FSHC Interrupt */
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MDM_IRQn = 20, /* 20 | Interrupt */
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RF_IRQn = 21, /* 21 | Interrupt */
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} IRQn_Type;
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#define __IRQFN __attribute__((section("ram_func")))
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/* Configuration of the Cortex-M0 Processor and Core Peripherals */
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#define __MPU_PRESENT 0 /*!< cm0ikmcu does not provide a MPU present or not */
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#define __NVIC_PRIO_BITS 2 /*!< cm0ikmcu Supports 2 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#if (1)
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#define __VTOR_PRESENT 1
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#include "core_cm0plus.h" /* Cortex-M0 plus processor and core peripherals */
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#else
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#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
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#endif
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#pragma diag_suppress 1296
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#endif
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/* SYSTICK - Cortex-M0 SysTick Register */
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typedef struct
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{
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__IO uint32_t CSR; //0x0, Control and Status
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__IO uint32_t RVR; //0x4, Reload Value
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__IO uint32_t CVR; //0x8, Current Value
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__IO uint32_t CALIB; //0xC, Calibration
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} TICK_TypeDef;
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/***************************************************************************/
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/* Peripheral Memory map */
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/***************************************************************************/
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#define BOOTROM_BASE ((uint32_t)0x00000000) // Boot Memory (4KB)
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#define FLASH_BASE ((uint32_t)0x18000000) // FLASH Controller (16MB)
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#define CACHE_REG_BASE ((uint32_t)0x19000000) // CACHE Reg (4KB)
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#define SRAM_BASE ((uint32_t)0x20003000) // SRAM Memory (20KB)
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#define RETN_BASE ((uint32_t)0x20008000) // BLE EM Memory (8KB)
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#define AHB_BASE ((uint32_t)0x40000000) // AHB Peripheral (64KB)
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#define APB1_BASE ((uint32_t)0x40020000) // APB Peripheral (64KB)
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#define APB2_BASE ((uint32_t)0x40030000) // APB Peripheral (64KB)
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/*
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* ==========================================================================
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* ---------------------------- Common MACRO ------------------------------
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* ==========================================================================
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*/
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/** @brief Enable interrupts globally in the system.
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* This macro must be used when the initialization phase is over and the interrupts
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* can start being handled by the system.
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*/
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#define GLOBAL_INT_START() __enable_irq() //__set_PRIMASK(0)
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/** @brief Disable interrupts globally in the system.
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* This macro must be used when the system wants to disable all the interrupt
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* it could handle.
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*/
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#define GLOBAL_INT_STOP() __disable_irq() //__set_PRIMASK(1)
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/** @brief Disable interrupts globally in the system.
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* This macro must be used in conjunction with the @ref GLOBAL_INT_RESTORE macro since this
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* last one will close the brace that the current macro opens. This means that both
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* macros must be located at the same scope level.
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*/
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#define GLOBAL_INT_DISABLE() \
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do { \
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uint32_t __l_irq_rest = __get_PRIMASK(); \
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__disable_irq();
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/** @brief Restore interrupts from the previous global disable.
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* @sa GLOBAL_INT_DISABLE
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*/
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//if (__l_irq_rest == 0) __enable_irq();
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#define GLOBAL_INT_RESTORE() \
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__set_PRIMASK(__l_irq_rest); \
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} while(0)
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#define WR_8(addr,value) (*(volatile uint8_t *)(addr)) = (value)
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#define WR_32(addr,value) (*(volatile uint32_t *)(addr)) = (value)
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#define RD_32(addr) (*(volatile uint32_t *)(addr))
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#include "rom.h"
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#endif //_B6X_H_
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