429 lines
16 KiB
C
429 lines
16 KiB
C
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/**
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****************************************************************************************
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*
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* @file dma.h
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*
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* @brief Header file - DMA Driver
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*
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****************************************************************************************
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*/
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#ifndef _DMA_H_
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#define _DMA_H_
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#include <stdint.h>
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#include <stdbool.h>
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#include "reg_dmachcfg.h"
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// warning: #61-D: integer operation result is out of range
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#pragma diag_suppress 61
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/*
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* DEFINES
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****************************************************************************************
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*/
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/// DMA Channel Index
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enum dma_channel
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{
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// Channel primary(CH0 ~ MAX-1)
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DMA_CH0 = 0,
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DMA_CH1,
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DMA_CH2,
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DMA_CH3,
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DMA_CH4,
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DMA_CH5,
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DMA_CH6,
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DMA_CH7,
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DMA_CH_MAX,
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// Channel alternate(CHx + MAX)
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DMA_CH_ALT = DMA_CH_MAX, // 0x08
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DMA_CH0_ALT,
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DMA_CH1_ALT,
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DMA_CH2_ALT,
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DMA_CH3_ALT,
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DMA_CH4_ALT,
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DMA_CH5_ALT,
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DMA_CH6_ALT,
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DMA_CH7_ALT,
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};
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/// DMA Peripheral Index
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enum dma_peripheral
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{
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DMA_PID_UART1_RX = 0,
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DMA_PID_UART1_TX = 1,
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DMA_PID_UART2_RX = 2,
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DMA_PID_UART2_TX = 3,
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DMA_PID_SADC = 4,
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DMA_PID_SPIM_TX = 5,
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DMA_PID_SPIM_RX = 6,
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DMA_PID_SPIS_TX = 7,
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DMA_PID_SPIS_RX = 8,
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DMA_PID_CTMR_CH1 = 9,
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DMA_PID_CTMR_CH2 = 10,
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DMA_PID_CTMR_CH3 = 11,
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DMA_PID_CTMR_CH4 = 12,
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DMA_PID_CTMR_TRIG = 13,
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DMA_PID_CTMR_UP = 14,
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DMA_PID_ATMR_CH1 = 15,
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DMA_PID_ATMR_CH2 = 16,
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DMA_PID_ATMR_CH3 = 17,
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DMA_PID_ATMR_CH4 = 18,
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DMA_PID_ATMR_TRIG = 19,
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DMA_PID_ATMR_UP = 20,
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DMA_PID_ATMR_COM = 21,
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DMA_PID_BTMR_UP = 22,
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DMA_PID_USB = 23,
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DMA_PID_MDM_TX = 24,
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DMA_PID_MDM_RX = 25,
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DMA_PID_MAX,
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};
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/// DMA Pointer of Peripheral Address
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enum dma_pointer
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{
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DMA_PTR_UART1_RX = 0x40023000, // ((uint32_t)&UART1->RBR),
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DMA_PTR_UART1_TX = 0x40023004, // ((uint32_t)&UART1->TBR),
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DMA_PTR_UART2_RX = 0x40024000, // ((uint32_t)&UART2->RBR),
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DMA_PTR_UART2_TX = 0x40024004, // ((uint32_t)&UART2->TBR),
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DMA_PTR_SADC_AUX = 0x40007014, // ((uint32_t)&SADC->AUX_ST),
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DMA_PTR_SADC_PCM = 0x40007018, // ((uint32_t)&SADC->PCM_DAT),
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DMA_PTR_SPIM_RX = 0x40004000, // ((uint32_t)&SPIM->RX_DATA),
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DMA_PTR_SPIM_TX = 0x40004004, // ((uint32_t)&SPIM->TX_DATA),
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DMA_PTR_SPIS_TX = 0x4000500C, // ((uint32_t)&SPIS->TX_DAT),
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DMA_PTR_SPIS_RX = 0x40005010, // ((uint32_t)&SPIS->RX_DAT),
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DMA_PTR_CTMR_CH1 = 0x40021044, // ((uint32_t)&CTMR->CCR1),
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DMA_PTR_CTMR_CH2 = 0x40021048, // ((uint32_t)&CTMR->CCR2),
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DMA_PTR_CTMR_CH3 = 0x4002104C, // ((uint32_t)&CTMR->CCR3),
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DMA_PTR_CTMR_CH4 = 0x40021050, // ((uint32_t)&CTMR->CCR4),
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DMA_PTR_CTMR_UP = 0x4002103C, // ((uint32_t)&CTMR->ARR),
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DMA_PTR_ATMR_CH1 = 0x40022044, // ((uint32_t)&ATMR->CCR1),
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DMA_PTR_ATMR_CH2 = 0x40022048, // ((uint32_t)&ATMR->CCR2),
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DMA_PTR_ATMR_CH3 = 0x4002204C, // ((uint32_t)&ATMR->CCR3),
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DMA_PTR_ATMR_CH4 = 0x40022050, // ((uint32_t)&ATMR->CCR4),
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DMA_PTR_ATMR_UP = 0x4002203C, // ((uint32_t)&ATMR->ARR),
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DMA_PTR_BTMR_UP = 0x4002003C, // ((uint32_t)&BTMR->ARR),
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DMA_PTR_MDM_TX = 0x40009030, // ((uint32_t)&MDM->EXT_TX_DAT),
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DMA_PTR_MDM_RX = 0x40009034, // ((uint32_t)&MDM->EXT_TX_DAT),
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};
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/// DMA State Machine
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enum dma_state
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{
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DMA_STA_IDLE = 0x0, // Idle
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DMA_STA_RD_CTRL = 0x1, // Read control
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DMA_STA_RD_SP = 0x2, // Read src pointer
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DMA_STA_RD_DP = 0x3, // Read dst pointer
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DMA_STA_RD_SRC = 0x4, // Read src data
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DMA_STA_WR_DST = 0x5, // Write dst data
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DMA_STA_WAIT_CLR = 0x6, // Wait request clear
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DMA_STA_WR_CTRL = 0x7, // Write control
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DMA_STA_STALLED = 0x8, // Stalled
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DMA_STA_DONE = 0x9, // Done
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DMA_STA_PER_SGTX = 0xA // Peripheral Scatter-Gather
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};
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/// DMA cycle ctrl mode
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enum cycle_ctrl
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{
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CCM_STOP = 0x0,
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CCM_BASIC = 0x1,
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CCM_AUTO_REQ = 0x2,
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CCM_PING_PONG = 0x3,
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CCM_MEM_SG = 0x4,
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CCM_MEM_SG_ALT = 0x5,
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CCM_PER_SG = 0x6,
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CCM_PER_SG_ALT = 0x7,
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};
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/// DMA unit for data-size and addr-inc
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enum unit_size
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{
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IN_BYTE = 0x0,
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IN_HALF = 0x1,
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IN_WORD = 0x2,
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IN_NONE = 0x3,
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};
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/// DMA channel control opcode
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enum chnl_ctrl
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{
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CHNL_DIS, // Disable
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CHNL_EN, // Enable
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CHNL_DONE, // Enable, Wait done
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};
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/// Bits field of DMA Transfers Configuration
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enum dma_trans_bfs
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{
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// DMA cycle ctrl mode - bit[2:0]
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DMA_TRANS_CCMODE_LSB = 0,
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DMA_TRANS_CCMODE_MSK = (0x07 << DMA_TRANS_CCMODE_LSB),
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// DMA next useburst - bit3
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DMA_TRANS_NEXTUB_POS = 3,
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DMA_TRANS_NEXTUB_BIT = (1 << DMA_TRANS_NEXTUB_POS),
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// DMA transfers cycles(1~1024)-1 - bit[13:4]
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DMA_TRANS_CYCLES_LSB = 4,
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DMA_TRANS_CYCLES_MSK = (0x3FF << DMA_TRANS_CYCLES_LSB),
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// DMA transfers can occur before rearbitrates - bit[17:14]
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DMA_TRANS_RPOWER_LSB = 14,
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DMA_TRANS_RPOWER_MSK = (0xF << DMA_TRANS_RPOWER_LSB),
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// DMA HPROT[3:1] when reads source data - bit[20:18]
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DMA_TRANS_SRCPROT_LSB = 18,
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DMA_TRANS_SRCPROT_MSK = (0x07 << DMA_TRANS_SRCPROT_LSB),
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// DMA HPROT[3:1] when writes destination data - bit[23:21]
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DMA_TRANS_DSTPROT_LSB = 21,
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DMA_TRANS_DSTPROT_MSK = (0x07 << DMA_TRANS_DSTPROT_LSB),
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// DMA source data size - bit[25:24]
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DMA_TRANS_SRCSIZE_LSB = 24,
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DMA_TRANS_SRCSIZE_MSK = (0x03 << DMA_TRANS_SRCSIZE_LSB),
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// DMA control source address increment - bit[27:26]
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DMA_TRANS_SRCINC_LSB = 26,
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DMA_TRANS_SRCINC_MSK = (0x03 << DMA_TRANS_SRCINC_LSB),
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// DMA destination data size, must same with source - bit[29:28]
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DMA_TRANS_DSTSIZE_LSB = 28,
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DMA_TRANS_DSTSIZE_MSK = (0x03 << DMA_TRANS_DSTSIZE_LSB),
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// DMA control source address increment - bit[31:30]
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DMA_TRANS_DSTINC_LSB = 30,
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DMA_TRANS_DSTINC_MSK = (0x03 << DMA_TRANS_DSTINC_LSB),
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};
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/// DMA Transfer Configuration struct
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typedef union
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{
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struct
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{
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uint32_t CYCLE_CTRL : 3; // Operating mode of the DMA cycle
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uint32_t NEXT_USEBURST : 1; // Next transfer use burst
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uint32_t N_MINUS_1 : 10; // Total number of DMA transfers - 1
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uint32_t R_POWER : 4; // How many DMA transfers can occur before controller rearbitrates
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uint32_t SRC_PROT_CTRL : 3; // Protect when controller reads the source data
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uint32_t DST_PROT_CTRL : 3; // Protect when controller writes the destination data
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uint32_t SRC_SIZE : 2; // Size of the source data, 0-byte 1-halfword 2-word
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uint32_t SRC_INC : 2; // Source address increment
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uint32_t DST_SIZE : 2; // Destination data size, must same with src_size
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uint32_t DST_INC : 2; // Destination address increment
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};
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uint32_t Word;
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} DMA_TRANS_CFG_Typedef;
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/// DMA Channel control data element
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typedef struct
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{
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// Source data end pointer
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uint32_t SRC_DATA_END_PTR;
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// Destination data end pointer
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uint32_t DST_DATA_END_PTR;
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// Control data configuration
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DMA_TRANS_CFG_Typedef TRANS_CFG_DATA;
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// Configuration reserved for reload
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DMA_TRANS_CFG_Typedef TRANS_CFG_RESV;
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} DMA_CHNL_CTRL_Typedef;
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/// DMA Channel control data struct
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typedef struct
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{
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// Channel primary
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DMA_CHNL_CTRL_Typedef PRI_CHNL[DMA_CH_MAX];
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// Channel alternate
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DMA_CHNL_CTRL_Typedef ALT_CHNL[DMA_CH_MAX];
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} DMA_CHNL_CTRL_STRUCT_Typedef;
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/// Global DMA Channel control data base pointer
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extern volatile DMA_CHNL_CTRL_STRUCT_Typedef dma_ctrl_base;
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/*
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* MACROS
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****************************************************************************************
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*/
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/// transfers cycle control mode
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#define TRANS_CCMODE(m) ((m) << DMA_TRANS_CCMODE_LSB)
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/// transfers cycles(1~1024)-1
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#define TRANS_CYCLES(c) ((c) << DMA_TRANS_CYCLES_LSB)
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/// transfers occur (before rearbitrates) = (1 << r), r>=10 means no arbitration occurs
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#define TRANS_RPOWER(r) ((r) << DMA_TRANS_RPOWER_LSB)
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/// transfers state of HPROT[3:1]: b0-privileged, b1-bufferable, b2-cacheable
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#define TRANS_SRCPROT(p) ((p) << DMA_TRANS_SRCPROT_LSB)
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#define TRANS_DSTPROT(p) ((p) << DMA_TRANS_DSTPROT_LSB)
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/// transfers unit size: 0-byte, 1-halfword, 2-word
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#define TRANS_UNIT(size) (((size) << DMA_TRANS_SRCSIZE_LSB) | ((size) << DMA_TRANS_DSTSIZE_LSB))
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/// transfers address increment: 0-byte, 1-halfword, 2-word, 3-no increment(address remains)
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#define TRANS_SRCINC(inc) ((inc) << DMA_TRANS_SRCINC_LSB)
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#define TRANS_DSTINC(inc) ((inc) << DMA_TRANS_DSTINC_LSB)
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/// transfers to read Peripheral(as SRC)
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#define TRANS_PER_RD(ccm, len, size, inc) \
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(TRANS_CCMODE(ccm) | TRANS_CYCLES((len)-1) | TRANS_UNIT(size) | TRANS_SRCINC(IN_NONE) | TRANS_DSTINC(inc))
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/// transfers to write Peripheral(as DST)
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#define TRANS_PER_WR(ccm, len, size, inc) \
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(TRANS_CCMODE(ccm) | TRANS_CYCLES((len)-1) | TRANS_UNIT(size) | TRANS_SRCINC(inc) | TRANS_DSTINC(IN_NONE))
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/// DMA Peripheral Configure
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// UARTx RX/TX
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#define DMA_UARTx_RX_INIT(chidx, x) dma_chnl_init(chidx, DMA_PID_UART##x##_RX)
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#define DMA_UARTx_RX_CONF(chidx, x, buff, len, ccm) \
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dma_chnl_conf(chidx, DMA_PTR_UART##x##_RX, (uint32_t)&(buff)[(len)-1], TRANS_PER_RD(ccm, len, IN_BYTE, IN_BYTE))
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#define DMA_UARTx_TX_INIT(chidx, x) dma_chnl_init(chidx, DMA_PID_UART##x##_TX)
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#define DMA_UARTx_TX_CONF(chidx, x, buff, len, ccm) \
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dma_chnl_conf(chidx, (uint32_t)&(buff)[(len)-1], DMA_PTR_UART##x##_TX, TRANS_PER_WR(ccm, len, IN_BYTE, IN_BYTE))
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// Common Timer CHx
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#define DMA_CTMR_CHx_INIT(chidx, x) dma_chnl_init(chidx, DMA_PID_CTMR_CH##x)
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#define DMA_CTMR_CHx_CONF(chidx, x, buff, len, ccm) \
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dma_chnl_conf(chidx, (uint32_t)&(buff)[(len)-1], DMA_PTR_CTMR_CH##x, TRANS_PER_WR(ccm, len, IN_WORD, IN_WORD))
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#define DMA_CTMR_IN_CHx_CONF(chidx, x, buff, len, ccm) \
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dma_chnl_conf(chidx, DMA_PTR_CTMR_CH##x, (uint32_t)&(buff)[(len)-1], TRANS_PER_RD(ccm, len, IN_WORD, IN_WORD))
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// Advance Timer CHx
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#define DMA_ATMR_CHx_INIT(chidx, x) dma_chnl_init(chidx, DMA_PID_ATMR_CH##x)
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#define DMA_ATMR_CHx_CONF(chidx, x, buff, len, ccm) \
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dma_chnl_conf(chidx, (uint32_t)&(buff)[(len)-1], DMA_PTR_ATMR_CH##x, TRANS_PER_WR(ccm, len, IN_WORD, IN_WORD))
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// SPI Master Role
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#define DMA_SPIM_TX_INIT(chidx) dma_chnl_init(chidx, DMA_PID_SPIM_TX)
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#define DMA_SPIM_TX_CONF(chidx, buff, len, ccm) \
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dma_chnl_conf(chidx, (uint32_t)&(buff)[(len)-1], DMA_PTR_SPIM_TX, TRANS_PER_WR(ccm, len, IN_BYTE, IN_BYTE))
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#define DMA_SPIM_RX_INIT(chidx) dma_chnl_init(chidx, DMA_PID_SPIM_RX)
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#define DMA_SPIM_RX_CONF(chidx, buff, len, ccm) \
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dma_chnl_conf(chidx, DMA_PTR_SPIM_RX, (uint32_t)&(buff)[(len)-1], TRANS_PER_RD(ccm, len, IN_BYTE, IN_BYTE))
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// SPI Slave Role
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#define DMA_SPIS_TX_INIT(chidx) dma_chnl_init(chidx, DMA_PID_SPIS_TX)
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#define DMA_SPIS_TX_CONF(chidx, buff, len, ccm) \
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dma_chnl_conf(chidx, (uint32_t)&(buff)[(len)-1], DMA_PTR_SPIS_TX, TRANS_PER_WR(ccm, len, IN_BYTE, IN_BYTE))
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#define DMA_SPIS_RX_INIT(chidx) dma_chnl_init(chidx, DMA_PID_SPIS_RX)
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#define DMA_SPIS_RX_CONF(chidx, buff, len, ccm) \
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dma_chnl_conf(chidx, DMA_PTR_SPIS_RX, (uint32_t)&(buff)[(len)-1], TRANS_PER_RD(ccm, len, IN_BYTE, IN_BYTE))
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// SADC Aux or PCM
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#define DMA_SADC_INIT(chidx) dma_chnl_init(chidx, DMA_PID_SADC)
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#define DMA_SADC_AUX_CONF(chidx, buff, len, ccm) \
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dma_chnl_conf(chidx, DMA_PTR_SADC_AUX, (uint32_t)&(buff)[(len)-1], TRANS_PER_RD(ccm, len, IN_HALF, IN_HALF))
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#define DMA_SADC_PCM_CONF(chidx, buff, len, ccm) \
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dma_chnl_conf(chidx, DMA_PTR_SADC_PCM, (uint32_t)&(buff)[(len)-1], TRANS_PER_RD(ccm, len, IN_HALF, IN_HALF))
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// MDM Ext Data
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#define DMA_MDM_TX_INIT(chidx) dma_chnl_init(chidx, DMA_PID_MDM_TX)
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#define DMA_MDM_TX_CONF(chidx, buff, len, ccm) \
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dma_chnl_conf(chidx, (uint32_t)&(buff)[(len)-1], DMA_PTR_MDM_TX, TRANS_PER_WR(ccm, len, IN_BYTE, IN_BYTE))
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#define DMA_MDM_RX_INIT(chidx) dma_chnl_init(chidx, DMA_PID_MDM_RX)
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#define DMA_MDM_RX_CONF(chidx, buff, len, ccm) \
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dma_chnl_conf(chidx, DMA_PTR_MDM_RX, (uint32_t)&(buff)[(len)-1], TRANS_PER_RD(ccm, len, IN_BYTE, IN_BYTE))
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/*
|
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* FUNCTION DECLARATION
|
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|
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****************************************************************************************
|
||
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|
*/
|
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|
|
|
||
|
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/**
|
||
|
|
****************************************************************************************
|
||
|
|
* @brief Init DMA Module
|
||
|
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*
|
||
|
|
****************************************************************************************
|
||
|
|
*/
|
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|
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void dma_init(void);
|
||
|
|
|
||
|
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/**
|
||
|
|
****************************************************************************************
|
||
|
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* @brief Deinit DMA Module
|
||
|
|
*
|
||
|
|
****************************************************************************************
|
||
|
|
*/
|
||
|
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void dma_deinit(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
****************************************************************************************
|
||
|
|
* @brief Init DMA Channel
|
||
|
|
*
|
||
|
|
* @param[in] chidx Channel index @see enum dma_channel, *only primary part*
|
||
|
|
* @param[in] chsel Selected peripheral @see enum dma_peripheral
|
||
|
|
*
|
||
|
|
****************************************************************************************
|
||
|
|
*/
|
||
|
|
void dma_chnl_init(uint8_t chidx, uint8_t chsel);
|
||
|
|
|
||
|
|
/**
|
||
|
|
****************************************************************************************
|
||
|
|
* @brief Deinit DMA Channel
|
||
|
|
*
|
||
|
|
* @param[in] chidx Channel index @see enum dma_channel, *only primary part*
|
||
|
|
*
|
||
|
|
****************************************************************************************
|
||
|
|
*/
|
||
|
|
void dma_chnl_deinit(uint8_t chidx);
|
||
|
|
|
||
|
|
/**
|
||
|
|
****************************************************************************************
|
||
|
|
* @brief Configure DMA Channel Control, then enable
|
||
|
|
*
|
||
|
|
* @param[in] chidx Channel index @see enum dma_channel, *incl alternate part*
|
||
|
|
* @param[in] src_ep Source data end pointer address, eg. (uint32_t)&buff[len-1]
|
||
|
|
* @param[in] dst_ep Destination data end pointer address
|
||
|
|
* @param[in] trans Transfer control value @see enum dma_trans_bfs or DMA_TRANS_CFG_Typedef
|
||
|
|
*
|
||
|
|
****************************************************************************************
|
||
|
|
*/
|
||
|
|
void dma_chnl_conf(uint8_t chidx, uint32_t src_ep, uint32_t dst_ep, uint32_t trans);
|
||
|
|
|
||
|
|
/**
|
||
|
|
****************************************************************************************
|
||
|
|
* @brief Reload tansfer control value that configured via dma_chnl_conf(), continue run.
|
||
|
|
*
|
||
|
|
* @param[in] chidx Channel index @see enum dma_channel, *only primary part*
|
||
|
|
*
|
||
|
|
* @return 'true' means auto turned to alt-channel *only ping-pong mode*
|
||
|
|
****************************************************************************************
|
||
|
|
*/
|
||
|
|
bool dma_chnl_reload(uint8_t chidx);
|
||
|
|
|
||
|
|
/**
|
||
|
|
****************************************************************************************
|
||
|
|
* @brief Read DMA Channel remain cycles
|
||
|
|
*
|
||
|
|
* @param[in] chidx Channel index @see enum dma_channel, *incl alternate part*
|
||
|
|
*
|
||
|
|
* @return Cycles of wait transfer, 0 means done
|
||
|
|
****************************************************************************************
|
||
|
|
*/
|
||
|
|
uint16_t dma_chnl_remain(uint8_t chidx);
|
||
|
|
|
||
|
|
/**
|
||
|
|
****************************************************************************************
|
||
|
|
* @brief Enable or disable DMA Channel after configured.
|
||
|
|
*
|
||
|
|
* @param[in] chidx Channel index @see enum dma_channel, *only primary part*
|
||
|
|
* @param[in] ctrl Control opcode @see enum chnl_ctrl
|
||
|
|
*
|
||
|
|
****************************************************************************************
|
||
|
|
*/
|
||
|
|
void dma_chnl_ctrl(uint8_t chidx, uint8_t ctrl);
|
||
|
|
|
||
|
|
/**
|
||
|
|
****************************************************************************************
|
||
|
|
* @brief Read DMA Channel done state, auto clear if be done.
|
||
|
|
*
|
||
|
|
* @param[in] chidx Channel index @see enum dma_channel, *only primary part*
|
||
|
|
*
|
||
|
|
* @return done state, true means done
|
||
|
|
****************************************************************************************
|
||
|
|
*/
|
||
|
|
bool dma_chnl_done(uint8_t chidx);
|
||
|
|
|
||
|
|
|
||
|
|
#endif// _DMA_H_
|