326 lines
17 KiB
C
326 lines
17 KiB
C
#ifndef _REG_AON_H_
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#define _REG_AON_H_
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#include "reg_base.h"
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//================================
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//BLOCK AON define
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#define AON_BASE ((uint32_t)0x40030000)
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#define AON_BACKUP0_ADDR_OFFSET 0x000
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#define AON_BACKUP1_ADDR_OFFSET 0x004
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#define AON_BKHOLD_CTRL_ADDR_OFFSET 0x008
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#define AON_BACKUP2_ADDR_OFFSET 0x00c
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#define AON_BLE_RTC_CTL_ADDR_OFFSET 0x010
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#define AON_SCAN_MODE_CTRL_ADDR_OFFSET 0x014
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#define AON_PMU_CTRL_ADDR_OFFSET 0x018
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#define AON_PMU_WKUP_CTRL_ADDR_OFFSET 0x01c
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#define AON_PMU_WKUP_ST_ADDR_OFFSET 0x020
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#define AON_PMU_ANA_CTRL_ADDR_OFFSET 0x024
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#define AON_XOSC16M_CTRL_ADDR_OFFSET 0x028
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//================================
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//BLOCK AON reg struct define
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typedef union //0x008
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{
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struct
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{
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uint32_t RC32K_MSB_TRIM_CFG: 4; // bit[3:0]
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uint32_t RC32K_LSB_TRIM_CFG: 10; // bit[13:4]
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uint32_t XOSC_EST_MODE: 1; // bit14 ---
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// 1: extarnal clock through XOSC16M_IN PAD into chip, and XOSC16M_OUT PAD is not driven by XOSC16M
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// 0: the XOSC16M_IN & XOSC16M_OUT are connected with crystal oscillator.
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uint32_t PIOA19_FUNC_SEL: 1; // bit15 ---
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// 0: pioa19 used as reset pin
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// 1: pioa19 used as GPIO
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// can't be reset by pin reset
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uint32_t AONLDO_TRIM_RUN: 4; // bit[19:16] --- LDOBK_TRIM,
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// inverter the high two bits
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// 0: 1.208
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// 1: 1.253
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// 2: 1.298
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// 3: 1.335
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// 4: 1.035
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// 5: 1.080
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// 6: 1.118
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// 7: 1.163
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// 8: 0.854
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// 9: 0.899
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// 10: 0.944
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// 11: 0.989
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// 12: 0.674
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// 13: 0.719
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// 14: 0.764
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// 15: 0.809
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uint32_t CORELDO_TRIM_RUN: 5; // bit[24:20] --- CORE LDO trim, used when ST_RUN
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uint32_t RSV_END: 7; // bit[31:25]
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};
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uint32_t Word;
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} AON_BKHOLD_CTRL_TypeDef; //0x008
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//================================
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#define AON_RC32K_MSB_TRIM_CFG_LSB 0
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#define AON_RC32K_MSB_TRIM_CFG_WIDTH 4
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#define AON_RC32K_LSB_TRIM_CFG_LSB 4
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#define AON_RC32K_LSB_TRIM_CFG_WIDTH 10
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#define AON_XOSC_EST_MODE_POS 14
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#define AON_PIOA19_FUNC_SEL_POS 15
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#define AON_AONLDO_TRIM_RUN_LSB 16
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#define AON_AONLDO_TRIM_RUN_WIDTH 4
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#define AON_CORELDO_TRIM_RUN_LSB 20
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#define AON_CORELDO_TRIM_RUN_WIDTH 5
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//================================
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typedef union //0x010
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{
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struct
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{
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uint32_t BLELOWCLK_EN: 1; // bit0
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uint32_t BLELOWCLK_SEL: 1; // bit1 --- BLE low power clock source select
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// 0: lsi clock, 32K
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// 1: HSE clock/500; 32K
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// set as 1 condtion:
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// chip is just in deepsleep mode, and makesure
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uint32_t RTC_EN: 1; // bit2
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// 0: RTC disable
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// 1: RTC enable
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uint32_t RSV_END: 29; // bit[31:3]
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};
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uint32_t Word;
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} AON_BLE_RTC_CTL_TypeDef; //0x010
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//================================
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#define AON_BLELOWCLK_EN_POS 0
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#define AON_BLELOWCLK_SEL_POS 1
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#define AON_RTC_EN_POS 2
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//================================
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typedef union //0x014
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{
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struct
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{
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uint32_t SCAN_MODE_REQ: 1; // bit0
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uint32_t SCAN_ZIP_CFG: 1; // bit1
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uint32_t RSV_END: 30; // bit[31:2]
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};
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uint32_t Word;
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} AON_SCAN_MODE_CTRL_TypeDef; //0x014
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//================================
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#define AON_SCAN_MODE_REQ_POS 0
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#define AON_SCAN_ZIP_CFG_POS 1
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//================================
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typedef union //0x018
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{
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struct
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{
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uint32_t AUTO_DIS_RC32K: 1; // bit0
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// when auto_dis_rc32k is 1
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// RC32K is auto disable when chip in poweroff state or deepsleep state
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// RC32K is auto enable when wakeup event happen for poweroff state or deepsleep
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// the RTC and BB WAKE LP can't used as wakeup source for DEEPSLEEP or poweroff
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// only GPIO or reset pin can be use
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uint32_t CORELDO_EN_RUN: 1; // bit1 --- When PMU is on ST_RUN, CORE LDO enable is controlled by coreldo_en_run
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uint32_t OSC_EN_RUN: 1; // bit2 --- When PMU is on ST_RUN, OSC enable is controlled by osc_en_run
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uint32_t RC32K_EN_RUN: 1; // bit3 --- only use when PMU in ST_RUN, RC32K
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uint32_t EM_PD_EN: 1; // bib4 ---
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// 1 : EM is power down
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// 0 : EN is power enable
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uint32_t EM_ACCESS_EN: 1; // bit5 ---
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// 1: EM is can be access
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// 0: EM is isolation
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// note:
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// em_access_en set as 0 before em_pd_en set as 1
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// em_access_en set as 1 after em_pd_en set as 0
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uint32_t RSV_NOUSE1: 2; // bit[7:6] --- Ignore me
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uint32_t POWEROFF_LOG: 1; // bit8 ---
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// when is 1, chip is powerup from POWEROFF state
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// else means chip is initial powerup or powerup from BOD event happen
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// cleared by poweroff_log_clr
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uint32_t EM_PD_ACK: 1; // bit9
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uint32_t RSV_END: 22; // bit[31:10]
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};
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uint32_t Word;
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} AON_PMU_CTRL_TypeDef; //0x018
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//================================
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#define AON_AUTO_DIS_RC32K_POS 0
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#define AON_CORELDO_EN_RUN_POS 1
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#define AON_OSC_EN_RUN_POS 2
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#define AON_RC32K_EN_RUN_POS 3
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#define AON_EM_PD_EN_POS 4
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#define AON_EM_ACCESS_EN_POS 5
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#define AON_POWEROFF_LOG_POS 8
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#define AON_EM_PD_ACK_POS 9
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//================================
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typedef union //0x01c
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{
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struct
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{
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uint32_t BLE_WKUP_SEL: 2; // bit[1:0] --- both use when deepsleep or poweroff state
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// 2'b00 disable ble wakeup
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// 2'b01: select ble_osc_en as wakeup source
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// 2'b10: select ble_radio_en as wakeup source
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// 2'b11: select ble_wakeup_lp as wakeup source
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// when poweroff mode, only ble_osc_en can be used
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uint32_t BLE_LATCH_N: 1; // bit2 ---
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// 0: latch the signal from BB to BLE LP counter
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// 1: enable the signal from BB to BLE LP counter
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// config as 0 before chip into poweroff mode
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// set as 1 after chip powerup and retain the BB state
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uint32_t IO_WKUP_EN: 1; // bit3 --- both use when deepsleep or poweroff state
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uint32_t RTC_WKUP_EN: 1; // bit4 --- both use when deepsleep or poweroff state
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uint32_t IO_LATCH_N: 1; // bit5 ---
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// 0: latch the GPIO control signal from core to AON
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// 1: enable the GPIO control signal from core to AON
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// config as 0 before chip into poweroff mode
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// set as 1 after chip powerup and retain the GPIO config
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uint32_t RC32K_TRIM_SEL: 1; // bit6 ---
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// 0: use rc32k_msb_trim_cfg and rc32k_lsb_trim_cfg control the RC32K freq
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// 1: use RC32K calib result control the RC32K freq
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uint32_t RSV_END: 25; // bit[31:7]
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};
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uint32_t Word;
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} AON_PMU_WKUP_CTRL_TypeDef; //0x01c
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//================================
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#define AON_BLE_WKUP_SEL_LSB 0
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#define AON_BLE_WKUP_SEL_WIDTH 2
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#define AON_BLE_LATCH_N_POS 2
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#define AON_IO_WKUP_EN_POS 3
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#define AON_RTC_WKUP_EN_POS 4
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#define AON_IO_LATCH_N_POS 5
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#define AON_RC32K_TRIM_SEL_POS 6
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//================================
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typedef union //0x020
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{
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struct
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{
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uint32_t IO_WKUP_ST: 1; // bit0
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uint32_t BLE_WKUP_ST: 1; // bit1
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uint32_t RTC_WKUP_ST: 1; // bit2
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uint32_t AON_PMU_INT: 1; // bit3
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uint32_t RSV_NOUSE1: 4; // bit[7:4] --- Ignore me
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uint32_t BOD12_OUT12_ST: 1; // bit8
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uint32_t LVD33_OUT12_ST: 1; // bit9
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uint32_t RSV_END: 22; // bit[31:10]
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};
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uint32_t Word;
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} AON_PMU_WKUP_ST_TypeDef; //0x020
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//================================
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#define AON_IO_WKUP_ST_POS 0
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#define AON_BLE_WKUP_ST_POS 1
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#define AON_RTC_WKUP_ST_POS 2
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#define AON_AON_PMU_INT_POS 3
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#define AON_BOD12_OUT12_ST_POS 8
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#define AON_LVD33_OUT12_ST_POS 9
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//================================
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typedef union //0x024
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{
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struct
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{
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uint32_t BK_BOD_TRIM: 3; // bit[2:0]
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uint32_t LDO_BOD_EN: 1; // bit3 --- BOD function:
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// detect the VDD12
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// when VDD12 < vth: BOD12_OUT12 is 1
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// else BOD12_OUT12 is 0
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uint32_t LDO_BOD_RST_EN: 1; // bit4
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uint32_t LDO12_IBSEL: 5; // bit[9:5]
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uint32_t LDO_LVD_EN: 1; // bit10
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uint32_t LDO_LVD_SEL: 3; // bit[13:11] --- BOD function:
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// detect the VDD33
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// when VDD33 < vth: LVD33_OUT12 is 1
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// else BOD12_OUT12 is 0
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uint32_t LDO_LVD_RST_EN: 1; // bit14
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uint32_t RSV_NOUSE1: 1; // bit15 --- Ignore me
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uint32_t ANA_RESV: 16; // bit[31:16] ---
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// [0] LDO_DPLL VREG12_EN1 TEST EN
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// [1] LDO_DPLL VREG12_EN2 TEST EN
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// [2] LDO_DPLL EN
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// [3] LDO32K TEST EN
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// [4] LDOCORE TEST EN
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// [7:5] LDODPLL_TRIM[2:0]
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// [8] DPLL2 ref clock select:0-OSC 16M, 1-RC 16M
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};
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uint32_t Word;
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} AON_PMU_ANA_CTRL_TypeDef; //0x024
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//================================
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#define AON_BK_BOD_TRIM_LSB 0
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#define AON_BK_BOD_TRIM_WIDTH 3
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#define AON_LDO_BOD_EN_POS 3
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#define AON_LDO_BOD_RST_EN_POS 4
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#define AON_LDO12_IBSEL_LSB 5
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#define AON_LDO12_IBSEL_WIDTH 5
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#define AON_LDO_LVD_EN_POS 10
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#define AON_LDO_LVD_SEL_LSB 11
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#define AON_LDO_LVD_SEL_WIDTH 3
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#define AON_LDO_LVD_RST_EN_POS 14
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#define AON_ANA_RESV_LSB 16
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#define AON_ANA_RESV_WIDTH 16
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//================================
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typedef union //0x028
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{
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struct
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{
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uint32_t EN_LDO_XOSC_REG: 1; // bit0
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uint32_t EN_LDO_SEL: 1; // bit1 --- EN_LDO_XOSC control select
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// 0: EN_LDO_XOSC is controlled by XOSC16M_EN
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// 1: EN_LDO_XOSC is controlled by EN_LDO_XOSC_REG
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uint32_t BYPASS_LDO_XOSC: 1; // bit2
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uint32_t RSV_END: 29; // bit[31:3]
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};
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uint32_t Word;
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} AON_XOSC16M_CTRL_TypeDef; //0x028
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//================================
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#define AON_EN_LDO_XOSC_REG_POS 0
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#define AON_EN_LDO_SEL_POS 1
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#define AON_BYPASS_LDO_XOSC_POS 2
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//================================
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//================================
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//BLOCK AON top struct define
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typedef struct
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{
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__IO uint32_t BACKUP0 ; // 0x000, valid-bit:16
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// can't be reset by pin reset, por12_bk_stb
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__IO uint32_t BACKUP1 ; // 0x004, valid-bit:8
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// can't be reset by pin reset por12_bk_stb
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__IO AON_BKHOLD_CTRL_TypeDef BKHOLD_CTRL ; // 0x008,
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// can't be reset by pin reset por12_bk_stb
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__IO uint32_t BACKUP2 ; // 0x00c, valid-bit:8
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// can be reset by pin reset
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__IO AON_BLE_RTC_CTL_TypeDef BLE_RTC_CTL ; // 0x010,
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__IO AON_SCAN_MODE_CTRL_TypeDef SCAN_MODE_CTRL ; // 0x014,
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// how to into scan mode
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// 1: CPU write this scan_mode_req
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// 2: wait 200us;
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__IO AON_PMU_CTRL_TypeDef PMU_CTRL ; // 0x018,
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__IO AON_PMU_WKUP_CTRL_TypeDef PMU_WKUP_CTRL ; // 0x01c,
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// set deepsleep poweroff wakeup source
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__I AON_PMU_WKUP_ST_TypeDef PMU_WKUP_ST ; // 0x020,
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__IO AON_PMU_ANA_CTRL_TypeDef PMU_ANA_CTRL ; // 0x024,
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__IO AON_XOSC16M_CTRL_TypeDef XOSC16M_CTRL ; // 0x028,
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} AON_TypeDef;
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#define AON (( AON_TypeDef *) AON_BASE)
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#endif
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