252 lines
12 KiB
C
252 lines
12 KiB
C
#ifndef _REG_MDM_H_
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#define _REG_MDM_H_
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#include "reg_base.h"
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//================================
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//BLOCK MDM define
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#define MDM_BASE ((uint32_t)0x40009000)
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#define MDM_REG0_ADDR_OFFSET 0x000
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#define MDM_REG1_ADDR_OFFSET 0x004
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#define MDM_CRC_PRESET_ADDR_OFFSET 0x008
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#define MDM_ACCESS_REG_ADDR_OFFSET 0x00c
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#define MDM_DAT_CFG_ADDR_OFFSET 0x010
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#define MDM_EXT_CTRL_ADDR_OFFSET 0x014
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#define MDM_RXSYNC_WIN_ADDR_OFFSET 0x018
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#define MDM_SLOT_SET_ADDR_OFFSET 0x01c
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#define MDM_FINECNT_SET_ADDR_OFFSET 0x020
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#define MDM_SLOTCNT_SET_ADDR_OFFSET 0x024
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#define MDM_FINECNT_ADDR_OFFSET 0x028
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#define MDM_SLOTCNT_ADDR_OFFSET 0x02c
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#define MDM_EXT_TX_DAT_ADDR_OFFSET 0x030
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#define MDM_EXT_RX_DAT_ADDR_OFFSET 0x034
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#define MDM_EXT_ST_ADDR_OFFSET 0x038
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//================================
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//BLOCK MDM reg struct define
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typedef union //0x000
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{
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struct
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{
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uint32_t RF_CHANNEL_NO: 6; // bit[5:0]
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uint32_t WHITENING_ON: 1; // bit6
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uint32_t CD1_EN: 1; // bit7
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uint32_t ACC_REG_EN: 1; // bit8
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uint32_t TX_INVERT: 1; // bit9
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uint32_t RX_INVERT: 1; // bit10
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uint32_t IQ_INVERT: 1; // bit11
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uint32_t LI_INVERT: 1; // bit12
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uint32_t LQ_INVERT: 1; // bit13
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uint32_t ACC_INVERT: 1; // bit14
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uint32_t FILT2_CLK_PH: 1; // bit15 --- no use
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uint32_t TXCLK_PH: 1; // bit16 --- use for RF CTRL sample the modem out TX_DATA
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// 0: use the posedge clk sample
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// 1: use the negedge clk sample
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uint32_t RSV_NOUSE1: 1; // bit17
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uint32_t DEBUG_MODE: 4; // bit[21:18] --- debug out select
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uint32_t TX_SCALE_EN: 1; // bit22
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uint32_t TX_SCALE_COEF_1M: 3; // bit[25:23] ---
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// tx_scale_coef[2]==1 : tx_out = tx_in *( 1 + tx_scale_coef[1:0]/16)
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// tx_scale_coef[2]==0 : tx_out = tx_in *( 1 - tx_scale_coef[1:0]/16)
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uint32_t TX_SCALE_COEF_2M: 3; // bit[28:26] ---
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// tx_scale_coef[2]==1 : tx_out = tx_in *( 1 + tx_scale_coef[1:0]/16)
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// tx_scale_coef[2]==0 : tx_out = tx_in *( 1 - tx_scale_coef[1:0]/16)
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uint32_t RSV_END: 3; // bit[31:29]
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};
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uint32_t Word;
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} MDM_REG0_TypeDef; //0x000
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//================================
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#define MDM_RF_CHANNEL_NO_LSB 0
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#define MDM_RF_CHANNEL_NO_WIDTH 6
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#define MDM_WHITENING_ON_POS 6
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#define MDM_CD1_EN_POS 7
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#define MDM_ACC_REG_EN_POS 8
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#define MDM_TX_INVERT_POS 9
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#define MDM_RX_INVERT_POS 10
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#define MDM_IQ_INVERT_POS 11
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#define MDM_LI_INVERT_POS 12
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#define MDM_LQ_INVERT_POS 13
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#define MDM_ACC_INVERT_POS 14
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#define MDM_FILT2_CLK_PH_POS 15
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#define MDM_TXCLK_PH_POS 16
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#define MDM_DEBUG_MODE_LSB 18
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#define MDM_DEBUG_MODE_WIDTH 4
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#define MDM_TX_SCALE_EN_POS 22
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#define MDM_TX_SCALE_COEF_1M_LSB 23
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#define MDM_TX_SCALE_COEF_1M_WIDTH 3
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#define MDM_TX_SCALE_COEF_2M_LSB 26
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#define MDM_TX_SCALE_COEF_2M_WIDTH 3
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//================================
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typedef union //0x004
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{
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struct
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{
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uint32_t MIN_MAG_CONF: 11; // bit[10:0]
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uint32_t RSV_NOUSE1: 1; // bit11
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uint32_t DRIFT_COR_SET: 2; // bit[13:12]
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uint32_t RSV_NOUSE2: 2; // bit[15:14]
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uint32_t IF_SHIFT: 13; // bit[28:16]
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uint32_t RSV_END: 3; // bit[31:29]
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};
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uint32_t Word;
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} MDM_REG1_TypeDef; //0x004
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//================================
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#define MDM_MIN_MAG_CONF_LSB 0
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#define MDM_MIN_MAG_CONF_WIDTH 11
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#define MDM_DRIFT_COR_SET_LSB 12
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#define MDM_DRIFT_COR_SET_WIDTH 2
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#define MDM_IF_SHIFT_LSB 16
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#define MDM_IF_SHIFT_WIDTH 13
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//================================
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typedef union //0x010
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{
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struct
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{
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uint32_t MDM_DAT_SET: 8; // bit[7:0]
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uint32_t MDM_DIRECT_SET: 1; // bit8 ---
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// 0: modem out use the gauss filter out
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// 1: modem out data is use mdm_dat_set[7:0]
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uint32_t RSV_END: 23; // bit[31:9]
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};
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uint32_t Word;
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} MDM_DAT_CFG_TypeDef; //0x010
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//================================
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#define MDM_MDM_DAT_SET_LSB 0
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#define MDM_MDM_DAT_SET_WIDTH 8
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#define MDM_MDM_DIRECT_SET_POS 8
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//================================
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typedef union //0x014
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{
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struct
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{
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uint32_t MDM_EXT_EN: 1; // bit0 ---
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uint32_t MDM_INT_EN: 5; // bit[5:1] ---
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// [0] mdm_tx_done interrupt en
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// [1] mdm_sync_err interrupt en
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// [2] mdm_slot_int interrupt en
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// [3] mdm_slot_over interrupt en
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// [4] mdm_sync_found interrupt en
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uint32_t MDM_SLOT_CNT_HOLD: 1; // bit6
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uint32_t MDM_SLOT_UPLOAD: 1; // bit7
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uint32_t MDM_SLOT_INT_CLR: 1; // bit8
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uint32_t RSV_END: 23; // bit[31:9]
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};
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uint32_t Word;
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} MDM_EXT_CTRL_TypeDef; //0x014
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//================================
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#define MDM_MDM_EXT_EN_POS 0
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#define MDM_MDM_INT_EN_LSB 1
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#define MDM_MDM_INT_EN_WIDTH 5
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#define MDM_MDM_SLOT_CNT_HOLD_POS 6
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#define MDM_MDM_SLOT_UPLOAD_POS 7
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#define MDM_MDM_SLOT_INT_CLR_POS 8
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//================================
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typedef union //0x01c
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{
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struct
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{
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uint32_t MDM_SLOT_WIN: 12; // bit[11:0] ---
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// slot window : (mdm_slot_win + 1 ) us
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// max slot window : 4096 us
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// default : 1ms
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uint32_t MDM_SLOT_OFF: 12; // bit[23:12] ---
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// slot interrput event offset
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uint32_t RSV_END: 8; // bit[31:24]
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};
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uint32_t Word;
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} MDM_SLOT_SET_TypeDef; //0x01c
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//================================
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#define MDM_MDM_SLOT_WIN_LSB 0
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#define MDM_MDM_SLOT_WIN_WIDTH 12
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#define MDM_MDM_SLOT_OFF_LSB 12
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#define MDM_MDM_SLOT_OFF_WIDTH 12
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//================================
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typedef union //0x038
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{
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struct
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{
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uint32_t MDM_TX_DONE: 1; // bit0 ---
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// when is 1
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// TX fifo is empty and last bit is sent out
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// cleared when tx_en is 0
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uint32_t MDM_SYNC_ERR: 1; // bit1 ---
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// when RX sync over time,
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// mdm_sync_err is 1
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// cleared by rx_en is 0
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uint32_t MDM_SLOT_INT: 1; // bit2 ---
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// cleared by mdm_slot_int_clr
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uint32_t MDM_SLOT_OVER: 1; // bit3 ---
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// cleared by mdm_slot_int_clr
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uint32_t MDM_SYNC_FOUND: 1; // bit4 ---
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// cleared by rx_en is 0
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uint32_t FIFO_EMPTY: 1; // bit5
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uint32_t FIFO_FULL: 1; // bit6
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uint32_t FIFO_NUM: 3; // bit[9:7]
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uint32_t MDM_SYNC_TIME: 12; // bit[21:10] ---
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// only valid when mdm_sync_found is 1
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// cleared when RX_EN is 0
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uint32_t RSV_END: 10; // bit[31:22]
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};
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uint32_t Word;
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} MDM_EXT_ST_TypeDef; //0x038
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//================================
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#define MDM_MDM_TX_DONE_POS 0
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#define MDM_MDM_SYNC_ERR_POS 1
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#define MDM_MDM_SLOT_INT_POS 2
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#define MDM_MDM_SLOT_OVER_POS 3
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#define MDM_MDM_SYNC_FOUND_POS 4
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#define MDM_FIFO_EMPTY_POS 5
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#define MDM_FIFO_FULL_POS 6
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#define MDM_FIFO_NUM_LSB 7
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#define MDM_FIFO_NUM_WIDTH 3
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#define MDM_MDM_SYNC_TIME_LSB 10
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#define MDM_MDM_SYNC_TIME_WIDTH 12
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//================================
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//================================
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//BLOCK MDM top struct define
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typedef struct
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{
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__IO MDM_REG0_TypeDef REG0 ; // 0x000,
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__IO MDM_REG1_TypeDef REG1 ; // 0x004,
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__IO uint32_t CRC_PRESET ; // 0x008,
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__IO uint32_t ACCESS_REG ; // 0x00c,
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__IO MDM_DAT_CFG_TypeDef DAT_CFG ; // 0x010,
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__IO MDM_EXT_CTRL_TypeDef EXT_CTRL ; // 0x014,
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__IO uint32_t RXSYNC_WIN ; // 0x018,
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// ext rx sync window :
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// (mdm_ext_rxsync_win + 1) us
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// max sync time : 4096 us
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// default is 2ms
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__IO MDM_SLOT_SET_TypeDef SLOT_SET ; // 0x01c,
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__IO uint32_t FINECNT_SET ; // 0x020,
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__IO uint32_t SLOTCNT_SET ; // 0x024,
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__I uint32_t FINECNT ; // 0x028,
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__I uint32_t SLOTCNT ; // 0x02c,
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__O uint32_t EXT_TX_DAT ; // 0x030,
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__I uint32_t EXT_RX_DAT ; // 0x034,
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__I MDM_EXT_ST_TypeDef EXT_ST ; // 0x038,
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} MDM_TypeDef;
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#define MDM (( MDM_TypeDef *) MDM_BASE)
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#endif
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