346 lines
12 KiB
C
346 lines
12 KiB
C
/**
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****************************************************************************************
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*
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* @file fshc.h
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*
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* @brief Header file - Flash Controlor(FSHC) Driver
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*
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****************************************************************************************
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*/
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#ifndef _FSHC_H_
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#define _FSHC_H_
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#include <stdint.h>
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#include <stdbool.h>
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/*
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* DEFINES
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****************************************************************************************
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*/
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typedef uint32_t flen_t; // uint16->32 reduce size 6vp 1118
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enum cache_region_size
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{
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CACHE_RS1K = 0x09,
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CACHE_RS2K = 0x0A,
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CACHE_RS4K = 0x0B,
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CACHE_RS8K = 0x0C,
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CACHE_RS16K = 0x0D,
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CACHE_RS32K = 0x0E,
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CACHE_RS64K = 0x0F,
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CACHE_RS128K = 0x10,
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CACHE_RS256K = 0x11,
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CACHE_RS512K = 0x12,
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};
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enum bit_num_mode
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{
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// 0/1: 1 bit spi mode
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SPI_MODE = 1,
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// 2: 2bits dual mode
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DUAL_MODE = 2,
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// 3: 4bits quad mode
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QUAD_MODE = 3,
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};
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/// Bits field of Cmd and Mode
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enum fshc_cmd_mode
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{
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// Command Code - bit[7:0]
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FCM_CMD_LSB = 0,
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FCM_CMD_MSK = 0xFF << FCM_CMD_LSB,
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// Line BitMode - bit[9:8]
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FCM_MODE_LSB = 8,
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FCM_MODE_MSK = 0x03 << FCM_MODE_LSB,
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// Special Bits - bit[11:10]
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// OTP read or write
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FCM_RWOTP_BIT = 1 << 10,
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// erase chip
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FCM_ERCHIP_BIT = 1 << 11,
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// R&W FIFO Type - bit[15:12]
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// pkt fill: 1 - next fragment, 0 - first of send-en
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FCM_NEXTPKT_BIT = 1 << 12,
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// multi-packet transmisson mode
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FCM_PACKETS_BIT = 1 << 13,
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// not wait complete
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FCM_NOTWAIT_BIT = 1 << 14,
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// enable suspend mode
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FCM_SUSPEND_BIT = 1 << 15,
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};
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// BitMode, default SPI_MODE
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#define FCM_MODE_DUAL (DUAL_MODE << FCM_MODE_LSB)
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#define FCM_MODE_QUAD (QUAD_MODE << FCM_MODE_LSB)
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// R&W FIFO Type
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#define FCM_TYPE_BLOCKING (0)
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#define FCM_TYPE_NOTWAIT (FCM_NOTWAIT_BIT)
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#define FCM_TYPE_SUSPEND (FCM_SUSPEND_BIT)
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#define FCM_TYPE_PKTSTART (FCM_PACKETS_BIT | FCM_NOTWAIT_BIT)
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#define FCM_TYPE_PKTNEXT (FCM_PACKETS_BIT | FCM_NEXTPKT_BIT)
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/// SBUS access flash send_ctrl register config
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enum addr_with_arg
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{
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// 2'b00/2'b11: address followed by idle
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IDLE_ADR_ARG = 0,
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// 2'b01: address followed by wdata
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SDAT_ADR_ARG = 1,
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// 2'b10: address followed by rdata
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RDAT_ADR_ARG = 2,
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};
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enum cmd_with_arg
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{
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// 3'b011: command followed by address
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SADR_CMD_ARG = 3,
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// 3'b101: command followed by wdata
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SDAT_CMD_ARG = 5,
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// 3'b110: command followed by rdata
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RDAT_CMD_ARG = 6,
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// others: command followed by idle
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IDLE_CMD_ARG = 0,
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};
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enum send_ctrl_bfs
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{
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// bit[1:0] - MCU transmit data bit number (@see enum bit_num_mode)
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SCTRL_DATA_BIT_MODE_LSB = 0,
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SCTRL_DATA_BIT_MODE_MSK = (0x03 << SCTRL_DATA_BIT_MODE_LSB),
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// bit[3:2] - MCU transmit address bit number (@see enum bit_num_mode)
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SCTRL_ADDR_BIT_MODE_LSB = 2,
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SCTRL_ADDR_BIT_MODE_MSK = (0x03 << SCTRL_ADDR_BIT_MODE_LSB),
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// bit[5:4] - MCU transmit command bit number (most support only 1bit, eg. GD)
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SCTRL_CMD_BIT_MODE_LSB = 4,
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SCTRL_CMD_BIT_MODE_MSK = (0x03 << SCTRL_CMD_BIT_MODE_LSB),
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// bit[7:6] - MCU address argument (@see enum addr_with_arg)
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SCTRL_ADDR_WITH_ARG_LSB = 6,
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SCTRL_ADDR_WITH_ARG_MSK = (0x03 << SCTRL_ADDR_WITH_ARG_LSB),
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// bit[10:8]- MCU command argument (@see enum cmd_with_arg)
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SCTRL_CMD_WITH_ARG_LSB = 8,
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SCTRL_CMD_WITH_ARG_MSK = (0x07 << SCTRL_CMD_WITH_ARG_LSB),
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};
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#define SEND_CTRL_CONF(datmode, adrmode, cmdarg, adrarg) \
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( ((datmode) << SCTRL_DATA_BIT_MODE_LSB) | ((adrmode) << SCTRL_ADDR_BIT_MODE_LSB) \
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| (SPI_MODE << SCTRL_CMD_BIT_MODE_LSB) /* command be mostly 1bit mode */ \
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| ((cmdarg) << SCTRL_CMD_WITH_ARG_LSB) | ((adrarg) << SCTRL_ADDR_WITH_ARG_LSB) )
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// command sent with address for READ, expect receive data.
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#define SCTRL_RD_DAT(datmode) SEND_CTRL_CONF(datmode, SPI_MODE, SADR_CMD_ARG, RDAT_ADR_ARG)
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// command sent with address and data for WRITE.
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#define SCTRL_WR_DAT(datmode) SEND_CTRL_CONF(datmode, SPI_MODE, SADR_CMD_ARG, SDAT_ADR_ARG)
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// SBUS control conf
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enum sbus_ctrl_cfg
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{
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// command sent without arguments for ENABLE Only.
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SCTRL_EN_CMD = SEND_CTRL_CONF(SPI_MODE, SPI_MODE, IDLE_CMD_ARG, IDLE_ADR_ARG),
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// command sent without arguments for READ, expect receive state value(l~4Bytes).
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SCTRL_RD_STA = SEND_CTRL_CONF(SPI_MODE, SPI_MODE, RDAT_CMD_ARG, IDLE_ADR_ARG),
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// command sent with state value(l~4Bytes) for WRITE.
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SCTRL_WR_STA = SEND_CTRL_CONF(SPI_MODE, SPI_MODE, SDAT_CMD_ARG, IDLE_ADR_ARG),
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// command sent without arguments for ERASE chip all.
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SCTRL_ER_CHIP = SEND_CTRL_CONF(SPI_MODE, SPI_MODE, IDLE_CMD_ARG, IDLE_ADR_ARG),
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// commnad sent with address for ERASE page/sector/bank part.
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SCTRL_ER_PART = SEND_CTRL_CONF(SPI_MODE, SPI_MODE, SADR_CMD_ARG, IDLE_ADR_ARG),
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// Read & Write date command in special mode.
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SCTRL_SIRD_DAT = SCTRL_RD_DAT(SPI_MODE),
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SCTRL_SIWR_DAT = SCTRL_WR_DAT(SPI_MODE),
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SCTRL_DLRD_DAT = SCTRL_RD_DAT(DUAL_MODE),
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SCTRL_DLWR_DAT = SCTRL_WR_DAT(DUAL_MODE),
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SCTRL_QDRD_DAT = SCTRL_RD_DAT(QUAD_MODE),
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SCTRL_QDWR_DAT = SCTRL_WR_DAT(QUAD_MODE),
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};
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enum adrcmd_bitlen_bfs
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{
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// bit[5:0] --- MCU adr cycle length,include dummy cycle, only 24 bit is valid
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ACBIT_ADR_LEN_LSB = 0,
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ACBIT_ADR_LEN_MSK = 0x1F << ACBIT_ADR_LEN_LSB,
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// bit[11:6] --- MCU cmd cycle length,include dummy cycle, only 8 bit is vaild,
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ACBIT_CMD_LEN_LSB = 6,
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ACBIT_CMD_LEN_MSK = 0x1F << ACBIT_CMD_LEN_LSB,
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};
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#define ACBIT_ADR_LEN(len) ((len) << ACBIT_ADR_LEN_LSB)
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#define ACBIT_CMD_LEN(len) ((len) << ACBIT_CMD_LEN_LSB)
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enum acbit_len_cfg
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{
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// 0x1C0 bit: cmd=8-1, adr=0
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ACBIT_SI_IDLE = ACBIT_CMD_LEN(7) | ACBIT_ADR_LEN(0x00),
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// 0x1D7 bit: cmd=8-1, adr=24-1, 0dumy=0
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ACBIT_SI_0DUMY = ACBIT_CMD_LEN(7) | ACBIT_ADR_LEN(0x17),
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// 0x1DF bit: cmd=8-1, adr=24-1, 1dumy=8
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ACBIT_SI_1DUMY = ACBIT_CMD_LEN(7) | ACBIT_ADR_LEN(0x1F),
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// 0x1CF bit: cmd=8-1, adr=24/2-1, 1dumy=4
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ACBIT_DL_1DUMY = ACBIT_CMD_LEN(7) | ACBIT_ADR_LEN(0x0F),
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};
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// SBUS access dummy
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enum sbus_dumy_cfg
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{
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// adr23 + NDUMY
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SBUS_SI_0DUMY = 0x17,
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// adr23 + 8(1DUMY)
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SBUS_SI_1DUMY = 0x1F,
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// adr24/2 - 1 + 4(1DUMY)
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SBUS_DL_1DUMY = 0xF,
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};
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/// IBUS access flash(only support read data) fshc ctrl configure
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enum cmd_len_dumy
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{
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// cmd(7) + dumy(0)
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CLEN_0DUMY = 7,
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// cmd(7) + dumy(8)
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CLEN_1DUMY = 15,
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};
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enum delay_set_bfs
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{
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// bit[5:0] --- hpm command length, default is 6'h1f,
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DLYSET_HPM_CLEN_LSB = 0,
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// bit[9:6] --- only use in qpi read cmd, default is 4'h7,
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DLYSET_CMD_LEN_LSB = 6,
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// bit[13:10]--- use in suspend/resume/exit_hpm cmd, default is 4'h7,
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DLYSET_0DUMY_CLEN_LSB = 10,
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// bit[15:14]--- CACHE transmit address bit number(@see enum bit_num_mode)
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DLYSET_ADDR_BIT_MODE_LSB = 14,
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// bit[17:16]--- CACHE transmit command bit number(@see enum bit_num_mode)
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DLYSET_CMD_BIT_MODE_LSB = 16,
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// bit[19:18]--- CACHE transmit data bit number(@see enum bit_num_mode)
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DLYSET_DATA_BIT_MODE_LSB = 18,
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};
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#define IBUS_CTRL_CONF(adrmode, datmode, hlen) \
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( ((adrmode) << DLYSET_ADDR_BIT_MODE_LSB) | (SPI_MODE << DLYSET_CMD_BIT_MODE_LSB) \
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| ((datmode) << DLYSET_DATA_BIT_MODE_LSB) | (CLEN_0DUMY << DLYSET_CMD_LEN_LSB) \
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| (CLEN_0DUMY << DLYSET_0DUMY_CLEN_LSB) | ((hlen) << DLYSET_HPM_CLEN_LSB) )
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// IBUS control conf
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enum ibus_ctrl_cfg
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{
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// spi read data via IBUS
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IBUS_SIRD_CFG = IBUS_CTRL_CONF(SPI_MODE, SPI_MODE, CLEN_0DUMY),
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//dual read data via IBUS
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IBUS_DLRD_CFG = IBUS_CTRL_CONF(SPI_MODE, DUAL_MODE, CLEN_0DUMY),
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//quad read data via IBUS
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IBUS_QDRD_CFG = IBUS_CTRL_CONF(SPI_MODE, QUAD_MODE, CLEN_0DUMY),
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//dual hpm read data via IBUS
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IBUS_DLRD_HPM = IBUS_CTRL_CONF(DUAL_MODE, DUAL_MODE, CLEN_1DUMY),
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//quad hpm read data via IBUS
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IBUS_QDRD_HPM = IBUS_CTRL_CONF(QUAD_MODE, QUAD_MODE, CLEN_1DUMY),
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};
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// IBUS access dummy
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enum ibus_dumy_cfg
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{
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IBUS_SI_0DUMY = 0x17,
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IBUS_SI_1DUMY = 0x1F,
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IBUS_DL_1DUMY = 0xF,
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IBUS_QD_1DUMY = 0xB,
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};
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/*
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* FUNCTION DECLARATION
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****************************************************************************************
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*/
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#if (ROM_UNUSED)
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/**
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****************************************************************************************
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* @brief Send control/enable command without value
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*
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* @param[in] cmd Command opcode(eg. FSH_CMD_RST_EN FSH_CMD_RESET FSH_CMD_EXIT_HMP
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* FSH_CMD_WR_EN FSH_CMD_WR_STA_EN)
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*
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****************************************************************************************
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*/
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void fshc_en_cmd(uint8_t cmd);
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/**
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****************************************************************************************
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* @brief Write value to flash state register
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*
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* @param[in] cmd Command opcode(eg. FSH_CMD_WR_STA)
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* @param[in] len Length of value, range 1~4 Bytes
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* @param[in] val State value, valid range 8/16/24/32bits by 'len'
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*
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****************************************************************************************
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*/
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void fshc_wr_sta(uint8_t cmd, uint8_t len, uint32_t val);
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/**
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****************************************************************************************
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* @brief Read value from flash state register
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*
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* @param[in] cmd Command opcode(eg. FSH_CMD_RD_ID FSH_CMD_RD_STA0 FSH_CMD_RD_STA1)
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* @param[in] len Length of value, range 1~4 Bytes
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*
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* @return value State value, valid range 8/16/24/32bits by 'len'
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****************************************************************************************
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*/
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uint32_t fshc_rd_sta(uint8_t cmd, uint8_t len);
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/**
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****************************************************************************************
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* @brief Perpare write data to flash
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*
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* @param[in] cmd fshc access cmd (example read cmd: 0x03)
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* @param[in] offset access flash addr offset
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* @param[in] len access flash data len, unit is byte
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* @param[in] sctrl access flash mode config(example: spi mode, dual mode...)
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* @param[in] acbit dummy cycle
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*
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****************************************************************************************
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*/
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void fshc_wr_cfg(uint8_t cmd, uint32_t offset, flen_t len, uint16_t sctrl, uint16_t acbit);
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flen_t fshc_wr_fifo(const uint32_t *data, flen_t wlen, uint16_t fcmd);
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/**
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****************************************************************************************
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* @brief Perpare read data from flash
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*
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* @param[in] cmd fshc access cmd (example read cmd: 0x03)
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* @param[in] offset access flash addr offset
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* @param[in] len access flash data len, unit is byte
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* @param[in] sctrl access flash mode config(example: spi mode, dual mode...)
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* @param[in] acbit dummy cycle
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*
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****************************************************************************************
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*/
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void fshc_rd_cfg(uint8_t cmd, uint32_t offset, flen_t len, uint16_t sctrl, uint16_t acbit);
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flen_t fshc_rd_fifo(uint32_t *buff, flen_t wlen, uint16_t fcmd);
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void fshc_xip_conf(uint8_t rdCmd, uint8_t adrBits, uint32_t dlySet);
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void fshc_hpm_conf(bool en, uint8_t crIdx, uint8_t crCmd);
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void fshc_erase(uint32_t offset, uint16_t fcmd);
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flen_t fshc_read(uint32_t offset, uint32_t *buff, flen_t wlen, uint16_t fcmd);
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flen_t fshc_write(uint32_t offset, const uint32_t *data, flen_t wlen, uint16_t fcmd);
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void fshc_cache_conf(uint32_t base_addr);
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void fshc_suspend_conf(uint8_t susCmd, uint8_t rsmCmd, uint16_t susTime, uint32_t rsmTime);
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#endif
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#endif // _FSHC_H_
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